Impact of Copper-Doped Titanium Dioxide Interfacial
Layers on the Interface-State and Electrical
Properties of Si-based MOS Devices
SEC¸K_IN AKIN and SAVAS¸ SO¨NMEZOG˘LU
The current study presents the interface-state and electrical properties of silicon (Si)-based metal-oxide-semiconductor (MOS) devices using copper-doped titanium dioxide (Cu:TiO2)
nanoparticles for possible applications as an interfacial layer in scaled high-k/metal gate MOSFET technology. The structural properties of the Cu:TiO2nanoparticles have been
ob-tained by means of X-ray diffraction (XRD), UV–Vis–NIR spectrometry, atomic force mi-croscopy, and scanning electron microscopy measurements; they were compared with pure TiO2
thin film. With the incorporation of Cu, rutile-dominated anatase/rutile multiphase crystalline was revealed by XRD analysis. To understand the nature of this structure, the electronic parameters controlling the device performance were calculated using current–voltage (I–V), capacitance–voltage (C–V), and conductance–voltage (G–V) measurements. The ideality factor (n) was 1.21 for the Al/Cu:TiO2/p-Si MOS device, while the barrier height /bwas 0.75 eV with
semi-log I–V characteristics. This is in good agreement with 0.78 eV measured by the Norde model. Possible reasons for the deviation of the ideality factor from unity have been addressed. From the C–V measurements, the values of diffusion potential, barrier height, and carrier concentration were extracted as 0.67, 0.98 eV, and 8.73 9 1013 cm3, respectively. Our results encourage further work to develop process steps that would allow the Cu-doped TiO2film/Si
interface to play a major role in microelectronic applications. DOI: 10.1007/s11661-015-3040-z
The Minerals, Metals & Materials Society and ASM International 2015
I. INTRODUCTION
I
Nthe last three decades, a considerable attention has been focused on research and development of metal-oxide-semiconductor (MOS) devices due to their supe-rior performance.[1] In general, MOS is an elementary structure used in the majority of electronic device technologies including capacitors, diodes, transistors, integrated circuits, and so on. The performance, relia-bility, and design of better-quality and faster MOS devices are strongly dependent on the presence of an oxide layer. The oxide material is one of the most significant cornerstones of the MOS devices. For over half a century, naturally or artificially grown silicon dioxide (SiO2) films have been preferred as the oxide layer in MOS devices. The insertion of a very thin SiO2 layer (from ~3 to 4 nm) between the metal and semi-conductor can make a dramatic difference in its func-tion. However, scaling down the thickness of a nearly perfect SiO2oxide layer has been limited by two main factors. One of the limiting factors is the unacceptably large leakage current due to further reductions in thickness. This results in a drastic increase in direct tunneling current between the oxide layer andsub-strate.[2]Utilization of MOS device with a thin dielectric film as oxide is an effective solution to reduce the high leakage current and improve device performance. Fur-thermore, the second limiting factor is the reliability issues associated with low dielectric constant (low-k). In addition, the breakdown voltage decreases with the decreasing thickness because the electric field increases at the same bias. Similar to the first solution, this scaling limit has also prompted intense basic research to find an alternative material with a higher dielectric constant (high-k) than SiO2to serve as the oxide. Therefore, high dielectric constant materials with higher physical thick-nesses and suitable electrical properties are actively being studied to overcome these limitations.
Among the high-k dielectric, insulating materials, titanium dioxide (TiO2) is one of the most promising candidates for replacing SiO2 due to the former’s high dielectric constant, stability, and so on.[3]TiO2occurs in nature with two allotropic forms—anatase and rutile. Both the anatase and rutile phases exhibit a tetragonal crystalline structure. The anatase phase attracts consid-erable interest due to its superior photocatalytic prop-erties,[4,5] whereas the rutile phase is a candidate for novel applications in optics and electronics including gate oxides of metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its high dielectric con-stant and refractive index.[6–8] Furthermore, an appro-priate cation substitution is sometimes a simple method to increase the relative dielectric constant.[9] Many studies were carried out on TiO2to optimize its further
SEC¸K_IN AKIN, Ph.D. Student, and SAVAS¸ SO¨NMEZOG˘LU, Associate Professor, are formerly with the Department of Materials Science and Engineering, Faculty of Engineering, Karamanoglu Mehmetbey University, Karaman, Turkey. Contact e-mail: svssonmezoglu@kmu.edu.tr
Manuscript submitted July 3, 2014. Article published online July 8, 2015
properties especially the addition of different dopants such as N,[10] Zn,[11] Mn,[12] Cu,[13] Al,[14] Te,[15] B,[16] Sb,[17]Au,[18]Au-Ag,[19]etc.
The Cu ions especially have lower vacancy-formation energy than the other dopants. This can be applied to structures, and allows semiconductors to form vacancy sites more easily. These vacancy sites help relax the structure; therefore, the electrical properties can be enhanced vs other systems. Cu is also an important dopant due to its higher electronic conductivity, low cost, and high availability.[20] Besides, Cu2+ doping effectively reduces the wide band gap of TiO2 by creating defects and Cu d-band states in TiO2that can also act as active electron trap centers to reduce the carrier recombination.[21] For example, Karatas¸ and Yakuphanog˘lu synthesized nanostructured Cu-doped CdO film with a sol–gel method and fabricated Al/Cu-doped CdO/p-Si heterojunction diode. As a result, they decided that Cu doping has a remarkable effect on the electrical properties of a heterojunction diode.[22]
There are no previous reports of Si-based MOS structures using Cu-doped TiO2as an interfacial layer. The aim of this study was to fabricate a high-quality Cu-doped TiO2/p-Si MOS structure and to study the feasi-bility and potential usefulness of Cu-doped TiO2oxide contact on semiconductors for use in Si-based MOS structures and barrier modifications. To understand the nature of this structure, we investigated some electronic parameters controlling the device performance including current–voltage (I–V) measurements, capacitance–volt-age (C–V), conductance–voltcapacitance–volt-age G=xð VÞ; and inter-face-state density ðNssÞ measurements. We also characterized the synthesized Cu-doped TiO2 nanoparti-cles using X-ray diffraction (XRD), scanning electron microscopy (SEM), atomic force microscopy (AFM), and UV–Vis–NIR spectrometry analysis.
II. EXPERIMENTAL PROCEDURE
A. Syntheses of Pure and Cu-Doped TiO2
The TiO2 solution was synthesized according to our previous work.[17,23,24] In a final step, copper (II) chloride was added in ethanol, and the solution was stirred magnetically for 2 hours. The resulting solution was added to the TiO2 solution and subjected to magnetic stirring for two additional hours. Finally, the Cu-doped TiO2 (Cu/Ti = 1/10) solution was aged at room temperature for 1 day before deposition.
B. Fabrication of Cu-Doped TiO2-based MOS Structures
The semiconductor wafer (p-type silicon) used in this study has a (1 0 0) orientation, 400-lm thickness, and resistivity ranging from 1 to 10 X cm. For the fabrication process, the Si wafer was degreased through the Radio Corporation of America (RCA) cleaning procedure. The RCA cleaning procedure involves three major steps that were used sequentially[25]: (1) Organic cleaning involves the removal of insoluble organic contaminants with 10-minute boiling in NH4OH + H2O2+ 6H2O solution. (2)
Oxide stripping involves removal of a thin silicon dioxide layer where metallic contaminants may have accumulated as a result of (1). The oxide on the front surface of the substrate was removed in HF:H2O (1:10) solution, and finally the wafer was rinsed in deionized water for 30 seconds. (3) Ionic cleaning involved a 10-minute boiling in HCl + H2O2+ 6H2O solution.
Next, it was subjected to a drying process in N2 atmosphere for a prolonged time. Then, the cleaned p-type silicon crystal was dipped into the solution. The dipping process was performed using the Holmarc Dip Coating unit, and the sample was dipped into the Cu:TiO2solution five times. After each dipping process, samples were subjected to repeated annealing processes at 573 K (300C) for 5-minute period. The prepared Cu:TiO2film was post-annealed at 1173 K (900C) for 1 hour in a furnace. Following the dipping process, high-purity (99.9 pct) aluminum (Al) was thermally evaporated from the tungsten filament using a shadow mask on to the whole back surface of the p-Si wafer at 107Torr. This rectified contact on the front surface of p-Si coated with Cu-doped TiO2. Rectifier dot contacts have a circular geometry with a diameter of about 1.0 mm. To obtain low-resistivity ohmic back contact, Si wafer was sintered at 853 K (580C) for 3 minutes in N2 atmosphere.[26] Thus, the Al/Cu:TiO2/p-Si MOS structure was obtained. These films have been also grown on quartz substrates under the same growth conditions to analyze the optical properties.
The thickness of the Cu-doped TiO2 on the Si semiconductor was 29.26 A˚ via ellipsometry. The dielec-tric constant of Cu-doped TiO2, ei, is calculated to be 39.96 from frequency measurement of the oxide capac-itance in the strong accumulation (Cox ¼ eie0A=d), where Cox= 94.9 pF in strong accumulation for 500-kHz frequency, e0is the permittivity of free space,[27]and A= 7.85 9 107m2.
C. Characterizations of Cu-doped TiO2Nanoparticles
and MOS Structure
The phase and crystallinity of the pure and Cu-doped TiO2metal oxide layers were investigated using Bruker D8 Advanced X-ray diffraction (XRD) ranging from 20 to 60 deg at a scanning rate of 0.01 deg s1. The morpholo-gies of the thin films were examined using a Zeiss LS– 10 scanning electron microscope (SEM) and Nanomag-netics atomic force microscope (AFM). The UV–Vis absorption and transmission measurements were also taken on a Shimadzu 3600 UV–Vis–NIR spectrophotometer. The current–voltage (I–V), capacitance–voltage (C–V), and conductance–voltage (G–V) measurements of the Al/Cu-doped TiO2/p-Si devices were performed with a Keithley 4200–SCS–CVU semiconductor characterization system.
III. RESULTS AND DISCUSSION
A. Structural Characterizations
Figure1 shows the XRD pattern of pure and Cu-doped TiO2nanoparticles deposited on silicon wafer. As
shown in Figure 1, the peaks of the sample can be clearly identified as anatase and rutile mixed-phase TiO2 (JCPDS No. 21-1272 and JCPDS No. 21-1276, respec-tively). This allowed a clear view of the characteristic peaks of the two different crystalline phases. These are marked on the pattern with A for anatase and R for rutile. In Figure1, we can recognize that the anatase characteristic peaks of the sample located at a 2h value of 25, 38, and 48 deg, and the rutile characteristic peaks located at 27, 36, 41, 54, and 56 deg are ascribed to (101), (004), and (200) crystal planes of anatase TiO2 and (110), (101), (111), (211), and (220) crystal planes of rutile phase TiO2, respectively. A similar result for the coexistence of anatase and rutile TiO2phases is reported by Ruan et al.[28] A characteristic peak of Cu is also detected in the pattern of Cu-doped TiO2film, suggest-ing that Cu was properly doped to the TiO2 matrix. However, one peak representing SiO2 plane appears, which corresponds to substrate as seen from the corresponding JCPDS files.
The main effect of Cu doping is a decrease in the anatase phase and, consequently, an increase in the rutile phase. This demonstrates that the Cu2+ dopant greatly inhibits the phase transformation from anatase to rutile. For the Cu-doped TiO2 film, Figure 1 also shows that the rutile peak (110) is stronger than that of the other rutile crystal planes in the mixed-phase TiO2. The presence of Cu dopant may increase (nucleation) and/or decrease lattice distortion/stress, which would alter the consequent peak intensities particularly if these dopants are preferentially present in one of the phases.[29] This result indicates that the (110) rutile phase TiO2has its preferred orientation. The degree of preferred orientation has been quantitatively calculated through a texture coefficient (TC). A sample with randomly oriented crystallite presents TC(hkl)=1; the
larger this value, the higher the abundance of crystallites oriented at the (hkl) direction. The results are shown in TableI, demonstrating that the highest TC was in rutile (110) plane for Cu:TiO2.
It is well known that dopant ions can enter the anatase lattice and influence the level of oxygen vacan-cies. This promotes or inhibits the transformation to rutile. The oxygen vacancies placed in anatase lattices act as a nucleation site for the anatase-to-rutile phase transformation.[30] If we consider defect formation by doping ions into the titania lattice, it can be supposed that dopants, which enter into the system by substituting for Ti4+, may either enhance or delay the transforma-tion from anatase to rutile depending on whether the number of oxygen vacancies is increased or de-creased.[31] When Cu ions substitute into the TiO2 structure, the charge of the Cu2+ ions should be balanced for an increase in oxygen vacancies facilitating an anatase-to-rutile phase transformation. This makes it unlikely to promote the transition to rutile.[32]
The crystallite sizes of pure and Cu-doped TiO2films can be deduced from the XRD line broadening, using the Scherrer’s formula:[33]
D ¼ 0:9 k
b cos h ½1
where D is the crystallite size (nm), k is the wavelength of CuKa radiation (nm), h is the Bragg angle (deg), and b is the full width at half-maximum (FWHM) of the diffraction peak. For a pure TiO2film, the crystallite size is 17.88 nm for the anatase (101) peak and 21.92 nm for the rutile (110) peak. Similarly, for the Cu-doped TiO2 film, the crystallite size was 20.88 nm for the anatase (101) peak and 31.95 nm for the rutile (110) peak. This increase is due to the substitution of the Cu2+ions into the host Ti4+sites—the radius of Cu2+ion (ionic radius 87 pm) is larger than the Ti4+ ion (ionic radius 74.5 pm).[34–36]
Moreover, the percentage of anatase/rutile phases in the mixed-phase of TiO2is calculated from XRD results by[37] 20 25 30 35 40 45 50 55 60 R (111) Cu-doped TiO 2 A Anatase TiO2 R Rutile TiO2 Cu SiO2 R (101) A (101) R (110) A (004) A (200) 2 theta (degree) Intensity (a.u.) pure TiO2 R (220) R (211)
Fig. 1—X–ray diffraction patterns of the pure and Cu-doped
TiO2nanocrystal samples on a Si wafer.
Table I. The Texture Coefficient Analysis of the Crystalline Structures for Anatase (A) and Rutile (R) Phases
Sample Phase (hkl) I/I0 TC
Pure TiO2 A (101) 1.00 2.25 (004) 0.45 0.20 (200) 0.70 0.55 R (110) 1.00 3.10 (101) 0.60 0.77 (111) 0.48 0.33 (211) 0.36 0.56 (220) 0.50 0.25 Cu:TiO2 A (101) 1.00 — R (110) 1.00 3.66 (101) 0.23 0.34 (111) 0.27 0.22 (211) 0.29 0.54 (220) 0.39 0.23
WR ¼
IR 0:884 IAþ IR
½2 where WR is the weight percentage of rutile phase, and IR and IA are the integrated intensity of rutile (d110) peak and the integrated intensity of anatase (d101) peak, respectively.[38] We calculated the ratio of rutile in the mixed-phase to be 47 pct for pure TiO2and 84 pct for Cu-doped TiO2.
B. Morphological Characterizations
The SEM microstructures at 30 and 100K times magnifications and AFM topography images were taken into consideration to investigate the surface morpholo-gies of pure and Cu-doped TiO2 films and depicted in Figures 2 and 3, respectively. As clearly seen in (Figure2(a)), the surface morphology of pure TiO2film reveals nanosized grains that partially combine to make a denser film. For the Cu-doped TiO2film, one can see that the synthesized particles are relatively monodis-perse with a tetragonal-shaped morphology and grain sizes of approximately a few hundreds of nanometers in diameter (Figure 2(b)). It is clear that Cu doping into the TiO2 structure improves the pure TiO2 film grain size. The grain diameters determined from SEM images are higher than that inferred from XRD analysis, suggesting that polycrystals are formed.
The evolutions of surface morphology, roughness, and granularity were also studied by AFM. The AFM images of pure and Cu-doped TiO2 films are homogeneously covered by many nanosized spherical particles (Figure3). The shapes and sizes of these particles are in good agreement with those in the SEM image (Figure2). The characteristics shown in Figure3 are parameterized by the root mean square (RMS) as well as the average roughness (Ra). The 2D image of pure TiO2 shows clusters with organized spherical particles; some of these particles are porous. From its corresponding 3D image,
an average surface roughness (roughness distribution) and RMS roughness were estimated to be 11.2 and 19.1 nm, respectively. Cu-doped TiO2 nanoparticles exhibit a smooth surface with uniform grains and higher density. The average grain size of Cu-doped TiO2 nanoparticles is 14.8 nm. The RMS roughness of the nanoparticles is estimated to be 11.8 nm.
C. Optical Characterizations
The optical properties of pure and Cu-doped TiO2 films were studied to investigate the effect of Cu doping. The transmittance and absorbance spectra of pure and Cu-doped TiO2films are shown in (Figure4(a)). As seen in this figure, the transmittance of pure TiO2 thin film decreases with incorporation of Cu. This suggests that doping decreases the transparency due to the increased absorption by free carriers.[39] This may be due to the fact that the pure TiO2film presents more voids than the Cu-doped TiO2 film, which may lead to a decrease in optical scattering.
Figure4(a) also indicates that the fundamental absorption edge is shifted slightly toward higher wave-lengths ranging from 350 to 400 nm with the incorpo-ration of Cu. For semiconductor nanoparticles, a quantum confinement effect is expected, and the absorp-tion edge will be shifted to a lower energy when the particle size increases.[40]Furthermore, with incorpora-tion of Cu dopants, an increased absorbance in the visible spectrum is also observed. The band gap energies Eg, shown in (Figure4(b)), have been resolved by applying the Tauc model in the high absorbance region. The estimated Eg of pure TiO2 was 3.52 eV, which is consistent with the reported value for anatase TiO2.[17] With incorporation of Cu dopant, the band gap energy decreased and was estimated to be 3.14 eV. Similar results were reported by Ly et al.[41] and Wongpisut-paisan et al.[42] for Cu-doped TiO2 prepared by wet chemical processing and sonochemical-assisted process, respectively. The results presented here confirm that a Fig. 2—SEM image of films at 30K times magnification: (a) pure; (b) Cu:TiO2. The inset is a partial enlarged view of a selected area (magnifica-tion; 100K times).
portion of Cu ion doped into the TiO2lattice alters the energy gap; the Cu doping causes an extension of TiO2 absorption into the visible region. Sahu et al.[21] exam-ined the red shift in the band gap as a function of Cu doping. They reported that absorption edge shifting and band gap reduction are controlled by the surface of the nanoparticles, lattice strain, and vacancies.
This is a well-known fact that band gap narrowing (BGN) has a significant importance on the electrical characteristics of the device. This change of approxi-mately 0.4 eV was due to the incorporation of Cu2+ ions into TiO2 crystal structure. In contrast to pure TiO2, the electrons are not directly excited to the conduction band because the unoccupied Cu2+ states and oxygen vacancies capture the electrons. Therefore, the sub-band states of Cu2+ and oxygen defects are responsible for the reduction of effective band gap of pure TiO2nanoparticles.[13,21] This suggests that Cu2+ forms sub-band states in the band gap of TiO2.[43]
D. The Electrical Characterizations of the Al/Cu-Doped TiO2/p-Si MOS Device
To understand whether or not a device has ideal behavior, an analysis of its experimental I–V character-istics have been performed by the forward-bias ther-mionic emission (TE) theory given as follows[44]:
I¼ I0 exp q Vð IRsÞ nkT 1 ½3 where n is the dimensionless ideality factor, V is the applied voltage across the rectifier contact, the IRs term is the voltage drop across the Rs of structure, q is the electronic charge, T is the absolute temperature, and k is the Boltzmann’s constant. Term I0 is the satu-ration current obtained from the intercept of the plot of lnðIÞ vs V at V = 0 is defined by I0¼ A AT2exp q /b;0 kT ½4 where A is the effective contact area, Aand /b;0are the effective Richardson constant of 32 A/cm2K2for p-type Si[45] and the zero bias barrier height (in units of eV), respectively.
Using Eq. [3], the value of /b;0can be expressed as
q/b;0¼ kT ln A A
T2
I0
½5
The ideality factor is the measure of abidance of the diode to pure TE theory. The value of the n is calculated Fig. 3—2D (left) and corresponding 3D (right) AFM topography images (in 2 9 2 lm areas) in ambient conditions: (a) pure; (b) Cu-doped TiO2.
from the slope of the linear portion of the semilog forward bias I–V characteristic and can be expressed as
n¼ q kT dV d ln Ið Þ IRs ½6
Under moderately forward bias condition, voltage across the series resistance (IRs) can be neglected. Equation [6] is then simplified to Eq. [7]:
n¼ q kT dV d ln Ið Þ ½7
Figure5 represents the experimental semi-log I–V characteristics of the Al/Cu:TiO2/p-Si MOS device at 300 K. As clearly shown in Figure 5, the MOS device has a good rectifying behavior. By using TE theory, n and /b;0 can be obtained from the slope and the current axis intercept of the linear region of the forward bias I–V plot, respectively. The values of the /b;0and n for the Cu-doped TiO2oxide layer-based MOS device are 0.75 eV and 1.21, respectively. This indicates that the effect of the series resistance in the linear region is not important.
The ideality factor of 1.21 is comparable with the values reported for pure and doped TiO2 oxide
layer-based MOS structures. Furthermore, this ideality factor is one of the lowest ideality factor values ever reported for pure and doped TiO2-based structures modified by a dopant. For example, So¨nmezog˘lu[7] reported that the barrier height and ideality factor of Dodecyl Benzene Sulfonic Acid (DBSA)-doped TiO2/p-Si MOS device were 0.53 eV and 1.28, respectively. In another work, So¨nmezog˘lu et al. reported the fabrication and electrical characterizations of an Sb-doped TiO2MOS device.[17] The values of /b and ideality factor n of this structure were 0.57 eV and 1.65, respectively. Compared with our previous reports, it is clear that Cu doping has the deepest impact on the titanium dioxide interfacial layer-based MOS structure. While the reverse saturation current I0 is determined from the y-intercept of semi logarithmic curve, and its value is 6.949 9 109A.
The deviation of the ideality factor from unity can be caused by the effects of bias voltage drop across the oxide layer, the distribution of interface states ðNssÞ localized at oxide/semiconductor interface, image force lowering at the interface, a wide distribution of low barrier height patches at metal/semiconductor interface, and series resistance.[44–47] The series resistance Rð sÞ is another key parameter of diode in the downward curvature of the forward bias I–V characteristics at a sufficiently high bias voltage. In this case, Cheung and Cheung verified another characterization technique to determine the electronic parameters of diode like barrier height, series resistance, and ideality factor.[47,48] The Cheung’s functions are expressed as[48]
dV d ln Ið Þ ¼ I Rsþ n kT q ½8 H Ið Þ ¼ V nkT q ln I A AT2 ½9 where H Ið Þ is given by H Ið Þ ¼ I RS þ n /b;0 ½10 300 400 500 600 700 800 900 1000 1100 0 10 20 30 40 50 60 70 80 (a) Absorbance (%) Cu:TiO 2 Pure TiO 2 Wavelength (nm) Transmittance (%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 (b) Cu:TiO2 Pure TiO2 hυ(eV) (α hυ ) 2x10 12 (e V .c m -2)
Fig. 4—(a) Optical transmission and absorbance spectra of pure and
Cu-doped TiO2 films. (b) The plots of ahmð Þ2vsphoton energy hmð Þ
for pure and Cu-doped TiO2films.
-1.0 -0.5 0.0 0.5 1.0 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 Current (A) Voltage (V)
Fig. 5—The forward and reverse bias current–voltage characteristics
The forward bias dV=dðln IÞ vs I and HðIÞ vs I characteristics obtained from Eqs. [7] and [8] for Al/ Cu:TiO2/p-Si MOS device are shown in Figure6. This clearly exhibits linear behavior and gives the value of RS as the slope, while y-axis intercept specifies nkT=q. The values of n and RSare calculated from the linear region of dV=dðln IÞ vs I plot as 2.41 and 368 X, respectively. After analyzing and comparing Figures 5 and 6, we found a slight change in n that is due to the existence of interface states at the junction, series resistance, and voltage drop across the interfacial layer.[17,46,49,50] This value of n is substituted in Eq. [9] and solved for the values of HðIÞ corresponding to the applied voltage V. Thus, in Figure 6, the HðIÞ vs I characteristic is shown as a straight line. Here the y-axis intercept gives /b, and the slope of the linear region represents a value of RS[48] that is equal to 340 X. Then using Eq. [5], a numerical value of /b is calculated, which is equal to 0.65 eV. These values are in good agreement with those found in conventional I–V characterization techniques. The Rs value calculated from HðIÞ vs I characteristics also agrees with what is seen in the dV=dðln IÞ vs I plot.
Furthermore, H. Norde proposed another character-ization technique to find out the magnitude of series resistance and barrier height.[51]The Norde’s equation is expressed as[52] F Vð Þ ¼V c kT q ln I Vð Þ A AT2 ½11 where F Vð Þ is the Norde function, c is an integer (di-mensionless) greater than n, and I Vð Þ is the current calculated from the I–V characteristic. Term c has been set to 2 for the Al/Cu:TiO2/p-Si MOS device. The barrier height of the devices is defined as follows:
/b;0¼ F Vð 0Þ þ V0
c
kT
q ½12
where F Vð 0Þ is the minimum value of the F Vð Þ, and V0 is the corresponding voltage. Figure 7demonstrates the F Vð Þ vs V plot of the Al/Cu:TiO2/p-Si MOS
device. The values of the series resistances have been calculated from Norde’s function for each of the struc-tures by using the following relation:
Rs¼ kT c nð Þ=qI 0
½13 where I0 is the current obtained from the F V
0
ð Þ. Using Eqs. [11] and [12], the barrier height and series resistance were obtained to be 0.78 eV and 1621.8 X, respectively. It is clearly seen that the difference in the /b;0 values obtained from both methods may be ascribed to the extraction from different regions of the forward-bias current–voltage plot.[53]Furthermore, the obtained val-ues for Rs for both methods are quite different from each other. This higher value of Rs obtained by Norde function can be attributed to the reduction of the exponential increase rate in current due to space charge injection into the oxide layer at higher forward-bias voltage.[54] Cheung’s model is applicable in the high-voltage region (nonlinear region in high high-voltage section) of the forward bias I–V characteristics while Norde’s model is applied to the full-voltage range of forward bias I–V characteristics of the junctions.[55]
The determination of the interface state density (Nss) is another key parameter for the information about the quality of the devices. The expression for the density of the interface states by considering the series resistance and voltage dependent ideality factor n Vð Þ is deduced by Card and Rhoderick[56]and given as
Nssð Þ ¼V 1 q ei dðn Vð Þ 1Þ es Wd ½14 where Wd is the width of the space charge region,[45]d (=29.2679 A˚) is the thickness of the interfacial layer, es (=11.8 e0), ei (=89 e0), and n Vð Þ ¼ V = kT=qð Þ ln I=Ið 0Þ are the permittivity of the semiconductor and interfacial layer and voltage-dependent ideality factor, respectively.[27] In addition, in a p-type semiconduc-tors, the energy of the interface states, Ess, with respect to the bottom of the valance band at the surface of semiconductor is expressed by[56] 2.0x10-44.0x10-46.0x10-48.0x10-41.0x10-31.2x10-31.4x10-3 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 H(I) (V) dV/d(lnI) (V) Current (A) 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10
Fig. 6—The experimental dV=dðln IÞ vs I and HðIÞ vs I plots obtained from forward bias current–voltage characteristics of the Al/Cu:TiO2/p–Si MOS device.
0.0 0.2 0.4 0.6 0.8 1.0 0.65 0.70 0.75 0.80 0.85 0.90 0.95 F(V) Voltage (V)
Fig. 7—Experimental F Vð Þ vs V curves of the Al/Cu:TiO2/p–Si MOS
Ess Ev¼ q/e qV ½15 where V is the voltage drop across the depletion layer, and /eis the effective barrier height. The energy density distribution profiles of the interface states as a function of Ess Evare extracted from the experimental forward bias I–V. Substituting the voltage-dependent values of n and the other parameters in Eq. [14], the Nss vs Ess Ev plot is presented in Figure 8. As simply seen in the Nssvs Ess Ev plot, the Nss values are reduced with the increasing Ess Ev values. The energy density distribu-tion of the interface states of the device changes from 2.56 9 1012cm2eV1in (0.67 Ev) to 0.24 9 1012cm2 eV1in (0.89 Ev). At any specific energy, it is noted that the densities of the Al/Cu:TiO2/p-Si MOS device interface states is lower than that of other TiO2 /p-Si MOS devices in the literature.
As can be seen from Figure9(a), the capacitance Cð Þ curve with three distinct regimes of accumulation– depletion–inversion is dependent on the bias voltage. The maximum capacitance has been observed in the accumulation region and has a value of 94.9 pF. Oxide thickness is also extracted from the accumulation capacitance and has a value of 29.2679 A˚. As expected, the values of measured capacitance from the gate to the p-Si associated with MOS structure decreases continu-ously with the increasing voltage due to the addition of the capacitance associated with the surface depletion region across the oxide as well as localized Nss at p-Si/ Cu:TiO2interface. Such behavior of the capacitance is attributed to particular distribution of interface states at p-Si/Cu:TiO2interfaces and Rs of structure.
In practice, experimental C–V characteristics are always different from ideal characteristics due the presence of non-ideal effects like interface trap and bulk charges. For the determination of non-ideal effects, it is necessary to calculate theoretical capacitance–voltage behavior of MOS capacitor. For this reason, the diffusion potential, barrier height, and carrier concentration are
estimated from 1=C2 V plots measured at the fre-quency of 500 kHz (Figure9(a)). The slope of the 1=C2 V curve corresponds to the localized carrier concentration. This is derived from the standard Schot-tky–Mott analysis[44]where the carrier concentration in a p-type material can be extracted in the depletion region by 1 C2¼ 2 Vð dþ VÞ qesA2NA ½16 where NA is the carrier concentration. Term Vd is the diffusion potential (equals to intercept of C2with the voltage axis) and is given by:
Vd¼ V0þ kT
q ½17
The value of the barrier height /b CVð Þ can be calculated from the C–V measurements by the following well-known equation: 0.65 0.70 0.75 0.80 0.85 0.90 0.95 0.0 0.5 1.0 1.5 2.0 2.5 3.0 N ss x 10 12 (c m -2 eV -1 ) E ss-Ev (eV)
Fig. 8—The density of interface state distribution profiles of the Al/ Cu:TiO2/p–Si MOS device at room temperature.
-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 (a) -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 0.2 0.4 0.6 0.8 1.0 Capacitance x 10 -11 (F) Voltage (V) 1/C 2x 10 20(1/F 2) Voltage (V) -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 0.50 0.75 1.00 1.25 1.50 1.75 2.00 (b) G/ ω x 10 -10 (F/s ) Voltage (V)
Fig. 9—(a) The C–V (inset) and 1=C2 V plots and (b) G=x V
characteristics of Al/Cu-doped TiO2/p–Si MOS device as measured at 500 kHz.
/b CVð Þ ¼ Vbi þ Vn ½18 The values of diffusion potential, barrier height, and carrier concentration for Al/Cu:TiO2/p-Si MOS device were 0.67, 0.98 eV, and 8.73 9 1013cm3, respectively. The higher values of barrier height, /b CVð Þ can be attributed to the sufficiently high frequency because the charge at the interface states cannot follow the AC signal at higher frequencies.
Figure 9(b) shows the forward and revers bias G=x V characteristics of the MOS structure measured at 500 kHz at room temperature. The G=x V characteristics show a similar behavior as the C–V curve. As seen in (Figure9(b)), while the conductance at negative voltages is decreased with the increasing voltage; at positive voltages, it is a constant. Moreover, Figure 9(b) shows that the values of the conductance have a peak near0.8 V. This behavior of corresponding peak in the G=x V curves lets us assign this variation to the electrical response of interface defect states. The possible reasons for this peak may the presence of deep states in the band gap, series resistance, and interface density states.[57]
IV. CONCLUSIONS
In conclusion, this study reports that Cu-doped TiO2materials are potential insulating/oxide layers in microelectronic applications. The results can be summa-rized as follows: (a) XRD analysis revealed that nanopar-ticles are anatase/rutile multiphase crystalline; Cu doping enhances the rutile phase ratio. (b) Through Cu doping, a tetragonal-shaped morphology with grain sizes of approx-imately a few hundreds of nanometers in diameter has been achieved. (c) A good-quality rectifying behavior of the Al/ Cu-doped TiO2/p-Si MOS structure has been estimated. The TE theory is ruled out for this device, and the n value was 1.21. (d) The barrier height and the series resistance determined by the Norde’s function are in good agreement with the values calculated from conventional I–V mea-surements. (e) The Nssvalue of the device was determined as it changes from 2.56 9 1012cm2eV1in (0.67 Ev) eV to 0.24 9 1012cm2eV1in (0.89 Ev) eV. (f) The Al/Cu-doped TiO2/p-Si MOS device showed an acceptable device performance and was more suitable for this type of device fabrication. Further studies are needed to determine the effects of the Cu-doped TiO2 interfacial layer on channel mobility, threshold voltage, and reliability.
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