DESIGN OF AN X-BAND GAN BASED
MICROSTRIP MMIC POWER AMPLIFIER
a thesis submitted to
the graduate school of engineering and science
of bilkent university
in partial fulfillment of the requirements for
the degree of
master of science
in
electrical and electronics engineering
By
Ula¸s ¨
Ozipek
February 2019
Design of an X-Band GaN Based Microstrip MMIC Power Amplifier By Ula¸s ¨Ozipek
February 2019
We certify that we have read this thesis and that in our opinion it is fully adequate, in scope and in quality, as a thesis for the degree of Master of Science.
Ekmel ¨Ozbay(Advisor)
Abdullah Atalar
U˘gur Baysal
Approved for the Graduate School of Engineering and Science:
Ezhan Kara¸san
ABSTRACT
DESIGN OF AN X-BAND GAN BASED MICROSTRIP
MMIC POWER AMPLIFIER
Ula¸s ¨Ozipek
M.S. in Electrical and Electronics Engineering Advisor: Ekmel ¨Ozbay
February 2019
RF power amplifiers are crucial components of modern radar and communication systems. However, their design poses some challenges due to device limitations in high power and high frequency regime, as well as inherent difficulties of designing for nonlinear large-signal device operation. Gallium Nitride (GaN) based High Electron Mobility Transistors (HEMT) are promising candidates due to their superior material qualities, high power densities and ability to operate up to mm-wave frequencies.
In this thesis, 0.25µm GaN on SiC microfabrication process of Bilkent Uni-versity Nanotechnology Research Center (NANOTAM) is presented. Transistor characterization procedure is demonstrated. Ideal transistor layout for design goals is selected and the transistor gate structure is optimized for X-band per-formance. A model library for microstrip passive circuit elements based on elec-tromagnetic simulations has been developed. Finally, design and measurements of an X-band microstrip Class AB two-stage Monolithic Microwave Integrated Circuit (MMIC) PA, based on the same process are presented in detail.
With die sizes smaller than 4.3 mm by 2.3 mm, fabricated MMICs operate at 8.5 - 11.5 GHz band with 24 dB small-signal gain. More than 13.5 W (41.3 dBm) output power (P6dB) and 31 - 38 % power-added efficiency are achieved
through-out the 8.5 - 11 GHz band in pulsed mode on-wafer measurements.
¨
OZET
X-BANT GAN TABANLI M˙IKROS
¸ER˙IT MMIC G ¨
UC
¸
Y ¨
UKSELTEC˙I
Ula¸s ¨Ozipek
Elektrik ve Elektronik M¨uhendisli˘gi, Y¨uksek Lisans Tez Danı¸smanı: Ekmel ¨Ozbay
S¸ubat 2019
RF ve mikrodalga g¨u¸c y¨ukselte¸cleri, g¨un¨um¨uz ileti¸sim ve radar sistemlerinin hayati bile¸senlerindendir. Bu bile¸senlerin tasarımları, y¨uksek g¨u¸c ve y¨uksek frekans rejimindeki aygıt kısıtlamaları ile; do˘grusal olmayan b¨uy¨uk-i¸saret ¸calı¸sma ko¸sullarında tasarımın kendi ¸cetinlikleriyle birlikte, ciddi zorlukları da beraberinde getirmektedir. Galyum Nitr¨ur (GaN) tabanlı y¨uksek elektron hareketlilikli transist¨or (HEMT) teknolojisi, y¨uksek g¨u¸c yo˘gunlukları, mm-dalga frekanslarına kadar ¸calı¸sabilme kabiliyetleri ve ¨ust¨un malzeme ¨ozellikleriyle, ¨
onemli bir potansiyel barındırmaktadır.
Bu ¸calı¸smada, Bilkent ¨Universitesi Nanoteknoloji Ara¸stırma Merkezi’nde (NANOTAM) geli¸stirilen 0.25µm Silisyum Karb¨ur (SiC) tabanlı GaN mikro-fabrikasyon prosesi, ve bu proses ile ¨uretilen aygıtların karakterizasyon adımları g¨osterilmi¸stir. X-bant uygulamalarına y¨onelik transist¨or ba¸sarımının iy-ile¸stirilmesi i¸cin ger¸cekle¸stirilen deneysel transist¨or serimi ve kapı geometrisi tarama ¸calı¸smaları sunulmu¸stur. Pasif devre elemanlarının elektro-manyetik ben-zetim tabanlı model k¨ut¨uphanesi olu¸sturulması anlatılmı¸stır. Son olarak, X-bant i¸cin tasarlanan monolitik mikrodalga entegre devre g¨u¸c y¨ukselteci tasarımı ve adımları, ayrıntılı bi¸cimde a¸cıklanmı¸stır. ¨Uretilen y¨ukselte¸c devrelerinin benze-tim ve ¨ol¸c¨um sonu¸cları payla¸sılarak yorumlanmı¸stır.
Yonga boyutları 4.3 mm x 2.3 mm’nin altında olan devreler, ¨ol¸c¨umlerde 8.5 GHz - 11.5 GHz frekans aralı˘gı boyunca 24 dB ¨uzerinde k¨u¸c¨uk i¸saret kazancı ver-mektedir. 13.5 Watt (41.3 dBm) ¨uzerindeki ¸cıkı¸s g¨u¸cleri ve %31 ile %38 arası g¨u¸c ekli verimlilik de˘gerleri, oda sıcaklı˘gında ger¸cekle¸stirilen darbeli mod ¨ol¸c¨umlerinde 6 dB kazan¸c kısılması altında, 8.5 GHz - 11 GHz bandı boyunca elde edilmi¸stir. Anahtar s¨ozc¨ukler : Galyum Nitr¨ur, MMIC, mikrodalga, X-bant, g¨u¸c y¨ukselteci.
Acknowledgement
I would like to extend my regards to my advisor Prof. Ekmel ¨Ozbay for providing the basis and opportunity for this work. To whom wits and discipline I can only aspire to. He was a continuous source of support and motivation throughout my studies while also permitting a vast space of freedom.
I wish to express my sincere gratitude to Prof. Abdullah Atalar, whose char-acter and ingenuity to seamlessly fuse profoundness and clarity, inspires many young people, and whom I was fortunate enough to be a student of.
My luck continued as I met Dr. ¨Ozlem S¸en as my first supervisor and later mentor, from whom I learned not only many technical aspects related to field, but also the virtues of kindness, diligence and humility.
I was surrounded by brilliant colleagues at NANOTAM RF group, with whom I enjoyed working and learning together. Although each one of its past and current members are sui generis, I should mention Arma˘gan G¨urdal for his collaboration during the course of this work. Without his ambition, scientific curiosity, in-quisitiveness and diligent efforts; many aspects of this work would be lacking. And also I should thank Muhammet Kavu¸stu for his comradeship throughout the journey of our studies.
I would like to celebrate the tireless efforts of NANOTAM fabrication team in pioneering the development of a GaN process.
Last but not least, I would like to offer my love and respects, to my family and friends, for providing me with inspiration and motivation, strength and passion.
I would also like to thank Prof. Baysal for reviewing this thesis.
I hereby dedicate this work to all my teachers and to people who work altru-istically towards dissemination and the pursuit of knowledge.
Contents
1 Introduction 1
2 Technology and Process Overview 3 2.1 Why GaN . . . 3 2.2 NANOTAM GaN Microfabrication Process Overview . . . 6
3 Transistor Characterization 13 3.1 DC Characterization . . . 13 3.2 RF Small-Signal Measurements . . . 16 3.3 Large-Signal (Load-Pull) Measurements . . . 18
4 MMIC Design 22
4.1 Transistor Optimization . . . 23 4.1.1 Layout Design/Comparison/Selection . . . 25 4.1.2 Parametric Gate Study . . . 29
CONTENTS vii
4.2 Topology Selection . . . 33
4.3 Passive Component EM Model Library . . . 37
4.4 Stability . . . 40
4.4.1 Even-Mode Stability . . . 41
4.4.2 Odd-Mode Stability . . . 44
4.5 Bias and Matching Networks . . . 49
4.5.1 Gate and Drain Bias Networks . . . 50
4.5.2 Output Matching . . . 52
4.5.3 Interstage Matching . . . 57
4.5.4 Input Matching . . . 60
5 Measurement Results and Analyses 65 5.1 Measurement Setup . . . 65
5.2 Measurement Results . . . 66
5.2.1 Small-Signal Measurements . . . 66
5.2.2 Power Sweep Measurements . . . 67
5.3 Discussions and Future Work . . . 71
List of Figures
2.1 Transistor technology performances in high frequency and high power domains . . . 4 2.2 Comparison of various performance metrics for transistor
semicon-ductor materials . . . 4 2.3 Thermal camera image from an operating GaN MMIC where
tem-perature peaks can be seen in gate finger/channel locations . . . . 5 2.4 A perspective drawing of the epitaxial and fabrication layers in a
GaN HEMT device . . . 7 2.5 Cross-sectional drawing of the wafer after GaN epitaxial growth
on SiC substrate at the beginning of fabrication . . . 8 2.6 Cross-section of wafer after ohmic metallization step . . . 9 2.7 Cross-section of wafer after first passivation step . . . 9 2.8 Cross-section of wafer after gate-foot dielectric opening and gate
metallization . . . 10 2.9 Cross-section of wafer after 2nd passivation step . . . 10
LIST OF FIGURES ix
2.10 Cross-section of wafer after TFR coating and gate field plate
met-allization . . . 11
2.11 Cross-section of wafer after Metal 1 layer coating and final dielec-tric passivation . . . 11
2.12 Cross-section of wafer after air-bridge formation and thick metal layer coating step . . . 12
2.13 Cross-section of wafer after finalization of backside fabrication pro-cess . . . 12
3.1 On-wafer DC-IV measurement setup . . . 13
3.2 IV curves of a 8×125µm HEMT . . . 14
3.3 gm and IDS vs Vgs curves of 8×125µm HEMTs . . . 15
3.4 Gate & drain leakage or breakdown characteristics of a 8×125µm HEMT . . . 15
3.5 CW on-wafer small-signal measurement setup . . . 16
3.6 RF measurement setup with DC pulsers and thermally controlled chuck for measurements in pulsed mode and at different temperatures 17 3.7 Input and output reflection coefficients of 8x125µm HEMTs . . . 17
3.8 Forward transmission characteristics of 8x125µm HEMTs under CW operation at room temperature . . . 18
3.9 Measurement and device reference planes . . . 18
3.10 Gt, PAE and Pout contours of an 8 × 125µm HEMT at 10 GHz under 3 dB gain compression . . . 19
LIST OF FIGURES x
3.11 Maury VNA based passive load-pull bench . . . 20 3.12 Block diagram of the vector network analyzer based load-pull system 20 3.13 Pout circles of an 8 × 125µm HEMT at 10 GHz under 3 dB gain
compression . . . 21
4.1 Photomask view of the microstrip transistor reticle . . . 23 4.2 Relation between total gate periphery and small-signal performance 25 4.3 Photomask views of 4 HEMTs with 1 mm gate peripheries and
different finger configurations . . . 26 4.4 Transistor layout parameters as marked on the SEM image are: a)
gate width, b) drain contact length, c) source contact length and d) drain-to-source distance or channel length . . . 27 4.5 Geometry of gate structures and corresponding surface electric field
intensities . . . 29 4.6 GT (green) and P3dB (red) load-pull contours (@ 10 GHz) of the
HEMT type with the best power density at 3 dB compression . . 32 4.7 GT (green) and P3dB (red) load-pull contours (@ 10 GHz) of the
HEMT type with better large-signal gain at 3 dB compression . . 32 4.8 Power sweep simulation of 2 stage MMIC with 2:4 topology at 10
GHz . . . 34 4.9 Power sweep fittings for a) 1st and b) 2nd stage transistors and
load-pull measurements superposed . . . 35 4.10 Power sweep simulation of 2 stage MMIC with 1:4 topology at 10
LIST OF FIGURES xi
4.11 Power sweep fittings for a) 1st and b) 2nd stage transistors and load-pull measurements superposed . . . 36 4.12 Power simulation results at 6 dB compression for 2:4 topology in
8.5 GHz - 11 GHz band . . . 36 4.13 Schematic and EM model data table view of spiral inductor . . . 37 4.14 EM substrate stack used in ADS . . . 38 4.15 Layout of the on-chip spiral inductor that correspond to 600 pH . 39 4.16 Comparison of inductor measurement and simulation results with
ideal inductor response . . . 39 4.17 Comparison of transmission line measurement and simulation
re-sults with ideal TL response . . . 40 4.18 Stability and MAG of a 8x125µm HEMT before stabilization . . . 42 4.19 Layout of the transistor with input stability cell . . . 43 4.20 Layout partitioning of 1st and 2nd stages in even-mode stability
tests . . . 43 4.21 Even-mode stability results of both stages . . . 44 4.22 One of the ADS schematics for calculating odd-mode impedances
and admittances at the input and output of 2nd stage transistors for odd-mode stabilization . . . 45 4.23 Schematic representations of odd excitation modes . . . 46 4.24 Highlighted odd-mode suppression resistors between the gate and
LIST OF FIGURES xii
4.25 Odd-mode impedances calculated at the input and output of 2nd stage transistors before odd-mode stabilization . . . 47 4.26 Odd-mode impedances calculated at the input and output of 2nd
stage transistors after odd-mode stabilization . . . 48 4.27 Odd-mode admittances calculated at the input and output of 2nd
stage transistors after odd-mode stabilization . . . 48 4.28 Schematic and merged layout views of a meandered microstrip
transmission line . . . 49 4.29 Frequency responses of schematic simulation vs. merged layout of
a meandered transmission line structure . . . 50 4.30 SEM images of on-chip inductors . . . 51 4.31 Layout view of the 1st stage gate and drain bias networks . . . 51 4.32 RF isolations of a) 1st stage gate and b) drain bias networks . . . 52 4.33 Pout (red) and GT (green) contours of the 8x125µm HEMT under
a) 0.5 dB and b) 4.5 dB GT compression . . . 53
4.34 Layout (a) and schematic (b) view of the 2nd stage transistors and OMN (TL electrical lengths in schematic view are @10GHz) . . . 54 4.35 Pout (red), transducer gain (green) and drain efficiency (blue)
con-tours of the 8x125µm HEMT at 3 dB compression at 10 GHz . . 54 4.36 Poutcontours of the 8x125µm HEMT at a) 8.5 GHz and b) 11 GHz
at 3 dB compression . . . 55 4.37 Load impedances presented to output stage transistors between
LIST OF FIGURES xiii
4.38 Impedance and phase asymmetry between OMN branches at 8.5 GHz - 11 GHz band . . . 56 4.39 Net insertion loss of output matching network at 8.5 GHz to 11
GHz band in dB scale . . . 57 4.40 Source-pull contours of an 8x125µm HEMT at 3 dB compression
at 9.5 GHz . . . 58 4.41 Schematic view of top half of the interstage matching network (TL
electrical lengths are given @10GHz) . . . 58 4.42 Layout view of top half of the interstage matching network . . . . 59 4.43 Output stage source (a) and driver stage load (b) impedances at
8.5 GHz - 11 GHz band . . . 59 4.44 Net insertion losses of interstage and output matching networks at
8.5 GHz to 11 GHz band in dB scale . . . 60 4.45 Schematic view of the input matching network (TL electrical
lengths are defined @10GHz) . . . 61 4.46 Layout view of the input matching network . . . 61 4.47 Source impedances presented to 1st stage transistors . . . 62 4.48 Calculated source-pull contours of an 8x125µm HEMT at 1 dB
compression at 9.5 GHz . . . 62 4.49 Small-signal simulation results of the design, performed using
S-parameter data of 30 HEMTs . . . 63 4.50 Schematic view of the finished design (given TL electrical lengths
LIST OF FIGURES xiv
4.51 Layout view of the finished design . . . 64
5.1 SEM view of a fabricated MMIC . . . 66
5.2 S-parameter measurement results of the fabricated 25 MMICs . . 66
5.3 S-parameter measurements (darker tones) and simulation results (lighter tones) superposed . . . 67
5.4 Output power, large-signal gain and PAE results of a fabricated MMIC at 8.5 GHz - 11 GHz band at 6 dB compression . . . 68
5.5 Power sweep measurements of MMICs at 8.5 GHz . . . 69
5.6 Power sweep measurements of MMICs at 10 GHz . . . 69
5.7 Power sweep measurements of MMICs at 11 GHz . . . 69
5.8 Comparison of large-signal measurements and power simulation results of a MMIC . . . 70
List of Tables
2.1 Semiconductor material properties comparison of Si, GaN, GaAs and SiC . . . 5 2.2 Baliga’s, Baliga’s High Frequency, Johnson’s and Keyes’ figure of
merits for Si, GaN, GaAs and SiC . . . 6 2.3 Properties of grown wafers and typical 2DEG performance . . . . 8
3.1 Overall DC, RF and load-pull results of 8x125µm HEMTs . . . . 21
4.1 GT U max, power and large-signal gain comparison of 1 mm HEMTs
with different finger configurations . . . 26 4.2 GT U max comparison of transistors @12 GHz with various drain &
source contact lengths versus channel lengths . . . 28 4.3 Load-pull results (at 10 GHz) of different contact length variants
are compared at 25◦C and 110◦C base temperatures . . . 28 4.4 Output power and large-signal gain comparison of transistors at
3 dB compression at 10 GHz, for gate geometries without SCFP structures . . . 31
LIST OF TABLES xvi
4.5 Large-signal performance comparison of gate geometries with SCFP structures at 10 GHz . . . 31 4.6 Design specifications of the power amplifier . . . 33 4.7 Power output and gain of the 8x125µm HEMT (at 3 dB
compres-sion) used in design . . . 33 4.8 2nd stage load impedances presented by OMN . . . 56 4.9 1st stage load and 2nd stage source impedances presented by ISMN 60 4.10 Load and source impedances presented to 1st stage transistors . . 62
5.1 Table of power measurement results of a fabricated MMIC at 8.5 GHz - 11 GHz band at 6 dB gain compression . . . 68 5.2 Performance comparison of measured MMIC results with
Chapter 1
Introduction
X-band of the electromagnetic spectrum is utilized by many radar and communi-cations systems. Power amplifiers (PA) are crucial elements of transmitter mod-ules in these systems since their output power and efficiency figures largely define overall system performance. Their design however, poses some challenges due to material limitations in high power and high frequency regime, as well as inherent difficulties of designing for nonlinear large-signal device operation. Ever increas-ing demand for better performance in modern systems, require higher output power and efficiency values, while keeping overall dimensions as small as possi-ble. Especially in systems where an array of modules are tightly stacked together, minimizing the chip size without compromising the output power capabilities be-comes imperative.
For these reasons, Gallium Nitride (GaN) based High Electron Mobility Tran-sistors (HEMT) are promising candidates due to their superior material qualities. High breakdown voltages of GaN transistors enable them to achieve high power densities. Their ability to withstand high junction temperatures during operation is a favored characteristic for PA design. Monolithic Microwave Integrated Cir-cuit (MMIC) technology is well suited to realize amplifier designs in a small die area with high performance, reliability and low cost [1]. Therefore, GaN MMICs receive a great deal of attention from academics and commercial field [2–12].
This thesis presents design and measurements of a 2-stage microstrip GaN power amplifier MMIC, fabricated using Bilkent University NANOTAM’s 0.25µm GaN on Silicon Carbide (SiC) process. MMICs operate at 8.5 - 11.5 GHz band with small-signal gain of 24 - 29 dB and pulsed mode output power of more than 14 W at 6 dB compression. These gain and output power figures are comparable with similar commercially available chips [13, 14].
Properties GaN on SiC HEMT technology are examined and a brief overview of NANOTAM microfabrication process is given in 2nd chapter. 3rd chapter details the DC, small-signal RF and large-signal characterization steps of transistors. De-tailed MMIC design process is described in chapter 4. Starting from the transistor selection and optimization phase, passive component model library development, amplifier topology selection, transistor stabilization and design of matching net-works are explained. In chapter 5, small-signal and power measurement results of MMICs are presented. Simulations are compared with measurement results and possible future works are discussed.
Chapter 2
Technology and Process
Overview
2.1
Why GaN
Gallium Nitride is a relatively new semiconductor material when compared to other mature technologies such as Gallium Arsenide and Silicon. However it quickly dominated several fields of applications (Fig. 2.1) where high frequency and high power are required [15] such as radars, transmitter systems, satellite communications, etc.
Popularity GaN technology in high power RF applications stems from its three main properties which distinguishes it from its rivals: high breakdown field, high saturation velocity and superior thermal properties (Fig. 2.2) [16].
Large bandgap of the GaN leads to higher breakdown field capability as seen on Table 2.1, which provides the opportunity for much higher operating voltages. Secondly, high saturation velocity in the two-dimensional electron gas (2DEG) channel in GaN devices allows for high current densities. Larger voltage and cur-rent swings means that RF output power capacity (which is simply approximated
Figure 2.1: Transistor technology performances in high frequency and high power domains
source: electronicdesign.com [15], original source: RF Micro Devices, Inc.
by the product of these two values) will be higher.
Figure 2.2: Comparison of various performance metrics for transistor semicon-ductor materials
source: semiconductor-today.com [16], original source: OKI Semiconductors
In addition to high RF power densities, GaN devices offer another crucial element of superior thermal properties. Although the thermal conductivity of bulk GaN is comparable to Silicon, its maximum operating temperature is much higher as seen in Table 2.1 [17, 18], which boosts its power handling capability and allows it to withstand much higher channel temperatures (Fig. 2.3).
Si GaN GaAs SiC Band gap energy, Eg, eV 1.1 3.4 1.4 2.9
Electric breakdown field, Ecrit,
106V/cm 300 3300 400 2500 Thermal Conductivity, k,
W/(K cm) 1.5 1.3 0.46 4.9 Electron Mobility, µ,
cm2/(V s) 1300 2000 5000 260
Saturation velocity, vsat,
107cm/s 1.0 2.5 1 2 Maximum operation
temperature, Tmax ◦C
200 700 300 500
Table 2.1: Semiconductor material properties comparison of Si, GaN, GaAs and SiC
In practical implementations of high power applications, GaN devices are often limited by their ability to dissipate heat through base substrate rather than their electronic properties [19]. Luckily, GaN lattice is suitable to grow on a number of substrate options with superb thermal properties such as Silicon Carbide (SiC) or diamond, both of which are very good thermal conductors. GaN-on-SiC de-vices have also the advantages of low lattice mismatch and relatively low thermal expansion mismatch, constituting ideal candidates for high power applications.
Figure 2.3: Thermal camera image from an operating GaN MMIC where tem-perature peaks can be seen in gate finger/channel locations
Advantages offered by GaN in various applications are reflected well in several figures of merits (FOM), listed in Table 2.2. Different figures of merits has been proposed to benchmark semiconductors by combining relevant material proper-ties with application specific merits of the semiconductors [17]. Johnson’s figure of merit (JFOM), which is a function of breakdown electric field and satura-tion electron velocity, indicates material’s suitability for high frequency and high power applications. Baliga’s FOM (BFOM) represents performance of transis-tors at low-frequency power switching applications. Another modified version of BFOM, Baliga’s high-frequency FOM (BHFOM) gives an idea about mate-rial’s high-frequency switching performance. Finally, the Keyes FOM (KFOM) considers thermal properties and current capabilities of material [18, 20].
Si GaN GaAs 4H-SiC BFMSi, nµcEcrit3 1 910 28 290
BHFOMSi, µcEcrit2 1 100 16 34
J F MSi, vsatEcrit/2 1 790 11 410
KFOM 1 1.8 0.45 5.1
Table 2.2: Baliga’s, Baliga’s High Frequency, Johnson’s and Keyes’ figure of merits for Si, GaN, GaAs and SiC
These figures of merits, together with high power densities and high opera-tion frequencies, justify the distinguished posiopera-tion GaN has in modern RF and microwave applications.
2.2
NANOTAM GaN Microfabrication Process
Overview
0.25µm AlGaN/GaN on SiC process of NANOTAM starts with carefully con-trolled epitaxial wafer growth on SiC substrate using metal organic chemical vapor deposition (MOCVD) system. GaN/AlGaN epitaxial structure mainly consists of AlN Nucleation, High Resistive (HR) GaN, Channel GaN, AlGaN Barrier, AlN Spike and GaN Cap layers from bottom to top, as seen in Fig 2.4.
Figure 2.4: A perspective drawing of the epitaxial and fabrication layers in a GaN HEMT device
First AlN nucleation layer of 20 nm-35 nm thickness is laid on SiC to improve surface roughness and ensure a more smooth transition from SiC to GaN lattice. This layer also helps with the vertical breakdown limit of the structure as it acts as an insulating dielectric layer.
A high resistive GaN buffer layer of 1.5µm thickness typically consisting of iron or carbon doped GaN acts as a buffer to restrict the movement of electrons to the channel above and prevent current leakages through the bulk material.
Channel GaN of approximately 100 nm thickness is the region where a high quality GaN crystal is grown to provide high mobility and saturation velocity, which together allow for higher saturation currents at the drain-to-source channel. An ultra thin AlN Spike layer of 1 nm is grown on channel GaN to increase charge confinement and mobility in the channel [21].
AlGaN barrier of 20 nm-25 nm thickness is grown to utilize the lattice mis-match between the GaN and AlGaN crystals to induce spontaneous piezoelectric polarization which creates a very thin layer of free electrons called Two Dimen-sional Electron Gas (2DEG) which constitutes the conductive channel between the drain and source contacts of the device, controllable by the applied gate voltage.
Finally, epitaxial growth phase of the wafers conclude with a 3 nm-5 nm thick GaN-Cap layer for better ohmic contact formation and for physically isolating AlGaN layer from outside factors for better device reliability.
General properties of grown wafers and typical 2DEG performances are illus-trated in Table 2.3.
Wafer and 2DEG Properties Surface RMS Roughness < 1 nm
Electron Mobility > 1800 cm2/(V s) Sheet Charge Density > 1 × 1013cm−2
Mesa Sheet Resistance < 400Ω/
Table 2.3: Properties of grown wafers and typical 2DEG performance Grown wafers as seen in Fig. 2.5 provide the basis for the microfabrication steps that follow.
Figure 2.5: Cross-sectional drawing of the wafer after GaN epitaxial growth on SiC substrate at the beginning of fabrication
First step in the fabrication process is ohmic contact formation for active devices. This layer forms the low resistance junctions at the metal-semiconductor interfaces. A metal stack consisting of Ti/Al/Ni/Au is deposited (Fig. 2.6) by an electron beam evaporator system with the respective thicknesses of 20 nm,
100 nm, 40 nm and 50 nm. The metal stack is annealed in a nitrogen atmosphere at 850◦C for 30 s.
Figure 2.6: Cross-section of wafer after ohmic metallization step
As the next step, mesa isolation etching is performed (Fig. 2.7) in which the AlGaN/GaN epitaxial layers forming the 2DEG are removed from everywhere on the wafer surface except active areas. This way all separate active devices are electrically isolated. Mesa etching is done with an inductively coupled plasma reactive ion etching (ICP-RIE) system by using Cl2/BCl3 plasma-based dry etch.
Mesa islands’ heights are measured approximately as 100 nm by surface profilome-ter. After ohmic contact formation and mesa isolation, a series of transmission line measurements are taken using the four-probe technique. The measured ohmic contact resistances are around 0.25Ω mm.
Figure 2.7: Cross-section of wafer after first passivation step
Surface of the sample is then passivated with a 75 nm thick Si3N4 layer grown
by a plasma-enhanced chemical vapor deposition (PECVD) system. The gate feet regions of the devices are patterned (Fig. 2.7) by dry etching this passivation layer using the ICP-RIE system with an SF6/Ar gas mixture.
(Fig. 2.8) with a Ni/Au metal stack using the electron beam evaporator system with thicknesses of 50 nm and 300 nm, respectively.
Figure 2.8: Cross-section of wafer after gate-foot dielectric opening and gate metallization
A passivation layer consisting of a 210 nm thick Si3N4 is deposited (Fig. 2.9)
as the next step, using the PECVD system. This Si3N4 layer also mechanically
supports the source connected field plate structures stationed above the gates. Then, dielectric openings for source and drain contacts, as well as the openings where the field plates connections and back-side via hole metals would be de-posited on, are formed (Fig. 2.9) by means of ICP-RIE dry etching system with SF6/Ar gas mixture.
Figure 2.9: Cross-section of wafer after 2nd passivation step
Afterwards, source connected field plate gate structure is patterned (Fig. 2.10) with direct electron-beam lithography and these regions are deposited with a Ti/Au metal stack (with thicknesses of 10 nm and 440 nm, respectively) for field plate metallization formation, using the electron beam evaporator system (Fig. 2.10). Resulting gate structure can be seen in Fig. 2.4.
A 86 nm TaN thin film resistor layer, which is used for realizing on-chip resis-tances in circuits and devices, is deposited (Fig. 2.10) by RF magnetron sputter
system.
Figure 2.10: Cross-section of wafer after TFR coating and gate field plate metal-lization
Thereafter, Ti/Au metal stack is deposited (Fig. 2.11) using the electron beam evaporator system with thicknesses of 10 nm and 1000 nm, respectively. This metal layer constitutes the metal contacts in transistor drain and source regions as well as forming the 1st metal layer of metal-insulator-metal capacitors. This is the first metal layer accessible to circuit designer and is used in various connections of the active and passive elements of integrated circuits.
Figure 2.11: Cross-section of wafer after Metal 1 layer coating and final dielectric passivation
3rd Si3N4 layer with a 240 nm thickness is deposited (Fig. 2.11) with PECVD
to form the dielectric material of the capacitors. The air-bridge post structures are utilized (Fig. 2.12) to form air bridges which reduce the parasitics and prevent short circuits at the metal-metal crossovers.
Thick metal layer of 4µm Au is coated (Fig. 2.12) as the main interconnec-tion layer using the electroplating system, concluding the front-side fabricainterconnec-tion process.
Figure 2.12: Cross-section of wafer after air-bridge formation and thick metal layer coating step
For the back-side fabrication process, the sample is grinded down to 100µm thickness and back-via holes are opened through the SiC substrate by means of ICP-RIE dry etching. Finally, 4µm thick Au layer is coated (Fig. 2.13) on the back side of the sample using the electroplating system. Walls of the via holes are also coated in the process. Ground connections of microstrip transistors and circuits are formed through these back-vias.
Figure 2.13: Cross-section of wafer after finalization of backside fabrication pro-cess
Chapter 3
Transistor Characterization
3.1
DC Characterization
A set of DC measurements are the first steps in HEMT characterization. On-wafer DC test setup is seen in Figure 3.1.
Figure 3.1: On-wafer DC-IV measurement setup
Formally, maximum saturated drain current, transconductance and IV curves can be used to derive a simple transistor model. In practice, DC measurements are also used to obtain an idea about device reliability and overall expected RF
and large-signal performance. A higher drain breakdown voltage high saturation current densities are associated with a higher maximum RF power, since they determine how large of a voltage and current swing can be maintained at the output of device [22]. Also gate and drain leakages are indicators of possible future device degradation under DC and RF stress.
Figure 3.2 is a typical IV curve for a 8×125µm GaN HEMT. The transistor has an Idss of 1 A equalling 1 A/mm which is considered standard for GaN HEMTs.
Figure 3.2: IV curves of a 8×125µm HEMT
Figure 3.3 is the transconductance curve of a 8×125µm GaN HEMT. Transcon-ductance which is defined as gm = dVdIgsd , is a measure of transistor output current
source’s sensitivity to small gate voltage perturbations. Thus, it gives an idea about small-signal gain transistor could produce without accounting for the par-asitic effects that will kick-in at higher frequencies.
Figure 3.4 is the breakdown characteristics of the device. The drain leakage was measured as 820µA while the HEMT was in pinched-off state (VGS = −6V ) and
the drain-to-source voltage was swept to 90 V. As seen from the measurement, drain leakage is smaller than 1 mA/mm which is considered as the accepted level for GaN HEMT devices.
Figure 3.3: gm and IDS vs Vgs curves of 8×125µm HEMTs
Figure 3.4: Gate & drain leakage or breakdown characteristics of a 8×125µm HEMT
3.2
RF Small-Signal Measurements
Characterizing the device behaviour is first done via small signal analysis. At higher frequencies, parasitics that are normally dormant at lower frequencies, be-come quite prominent and affect the input and output impedance of these devices. These reactance/susceptances need to be resonated so that maximum gain can be obtained from the devices. Therefore, frequency responses of the transistors are measured using vector network analyzers. Small-signal linear behaviour of devices are captured with these S-parameter measurements.
Figure 3.5 is the small signal setup used for continuous wave S-parameter measurements.
Figure 3.5: CW on-wafer small-signal measurement setup
At various operation conditions such as bias point, temperature and operation mode -e.g. pulsed or CW-, device behaviour can change, therefore at different conditions, these linear behaviours are separately characterized using small-signal measurements. The superposition of all these behaviours are expected to conform to the design specifications.
Probe station with thermally controlled chuck in the setup in Figure 3.6 and DC pulsers are used for pulsed S-parameters measurements, as well as measure-ments at various base temperatures.
Figure 3.6: RF measurement setup with DC pulsers and thermally controlled chuck for measurements in pulsed mode and at different temperatures
Bulk results of S-parameter measurements for 8x125µm HEMTs are shown in Figure 3.7 and Figure 3.6.
(a) (b)
Figure 3.7: Input and output reflection coefficients of 8x125µm HEMTs Since on-wafer calibration of the vector-network-analyzer (VNA) brings mea-surement reference planes to the probe tips, meamea-surement results of devices also include RF probe pads and extra transmission lines between the pads and the device reference planes as shown in Figure 3.9. In other words, parasitic pad capacitances and open end effects together with the transmission line between
(a) Multiple |S21| graphs of HEMTs (b) M AG and GT U max graphs of HEMTs
Figure 3.8: Forward transmission characteristics of 8x125µm HEMTs under CW operation at room temperature
probe’s tip to the designated transistor should be taken into account [23].
Figure 3.9: Measurement and device reference planes
Therefore, the tranmission lines and RF measurement pads between reference planes are EM simulated and de-embedded from the overall measurement [24].
3.3
Large-Signal (Load-Pull) Measurements
Optimum load impedances for maximum power and maximum gain are the same for low input powers. But as the devices are driven to large-signal operation, due to the non-linear characteristics of the transistor, optimal output impedances for
gain and power become gradually separated [25] (Examined in more detail in Section 4.5.2 and 4.5.3). Figure 3.10 shows the load-pull contours of Gt, PAE
and Pout at 3 dB compression at 10 GHz for an 8 × 125µm HEMT. It should be
noted that the circles for all these parameters converge on different impedances.
Figure 3.10: Gt, PAE and Pout contours of an 8 × 125µm HEMT at 10 GHz under
3 dB gain compression
Since, main function of PAs is to deliver highest possible power, aside from other performance merits, these power contours need to be modelled to receive more power out of the device at the given conditions. To achieve this, either a large signal model ought to be available, or these impedances need to be empri-cally determined. In our design methodology, load-pull measurements are used to determine these impedances. Figure 3.11 is the Vector Network Analyzer (VNA) based Maury passive load-pull system that is used for large-signal transistor char-acterization. Tuners operate from 0.8 GHz to 18 GHz.
This is a vector based load-pull system, block diagram of which can be seen in Fig. 3.12. Incident and reflected power waves at the input and output of the DUT are sampled via the low-loss couplers connected immediately before the tuners. That way available and delivered input and output powers can be directly calculated via a and b waves; as well as the source, input, output and load impedances at the DUT reference planes.
Figure 3.11: Maury VNA based passive load-pull bench
Figure 3.13 is the output contours of a typical 8 × 125µm HEMT measured at 10 GHz under 3 dB gain compression.
Figure 3.13: Pout circles of an 8 × 125µm HEMT at 10 GHz under 3 dB gain
compression
Overall HEMT performance parameters can be seen in the table below. Parameter Symbol Typical value Max. Drain Current Idss 1000 mA/mm
Peak Transconductance gm 300 mS/mm Breakdown Voltage Vbr >90 V
Gate Threshold Voltage Vth −3.5 V
On Resistance Ron 2.2 Ω mm
Max. Available Gain @10 GHz Gmax 17 dB
Quiescent Drain Voltage VDD 28 V
Power Density P3dB 5.5 W/mm
Chapter 4
MMIC Design
In this chapter, design steps of the 2-stage MMIC PA are described in detail. Our aim for this design was to achieve more than 13.5 W output power under pulsed mode operation with less than 6 dB gain compression. Also a minimum large-signal gain of 19 dB was targeted. Design is based on the S-parameter and load-pull measurement data of transistors. Small-signal simulations, layout design and EM simulations are carried out in Keysight’s Advanced Design System (ADS) software. Bulk analysis of vector based load-pull measurements of transistors and power sweep simulations for MMICs are performed on MATLAB.
In order to achieve design goals with minimum amount of transistors (hence with greater efficiency and smaller circuit area), optimal transistor size, layout and gate structure have been investigated first. After the ideal transistor and gate type has been determined, preliminary small-signal and power analyses have been performed to decide the possible amplifier topologies for specified design goals. As the first step of the amplifier design, stability circuits are added to selected transistors for even-mode stability of both stages. Next, gate and drain bias lines with sufficient in-band RF grounding and isolation are realized. Output, inter-stage and input matching networks have been designed in sequence. Parametric optimization for the merged layouts of matching networks have been performed to account for any unwanted effects coming from discontinuities and EM couplings.
Finally, even and odd-mode stability analyses for the circuit have been done and additional stability elements have been added to reinforce stability under various bias, temperature and pulse conditions.
4.1
Transistor Optimization
For investigating optimal transistor size, layout and gate structure for X-band performance, a HEMT development photomask is prepared (Fig. 4.1); where transistors of different gate peripheries with varying gate widths and number of fingers are placed.
Figure 4.1: Photomask view of the microstrip transistor reticle
In the same photomask, also a parametric study of various gate geometries has been conducted, since transistor gate structure is crucial in determining overall transistor performance.
Both small-signal and large-signal measurements are taken into account when comparing performances of various types of transistors. However due to the time consuming nature and more demanding infrastructure requirements of load-pull measurements, automated small-signal measurements are used to initially sift through the large number of transistor variants and minimize the number of candidates to a manageable size.
For the purpose of ranking small-signal performances of transistors among themselves, their maximum available gains are compared; which equals to the gain when simultaneous perfect conjugate match is achieved at the input and output of transistors. Instead of the widely used criterion of Maximum Available Gain (M AG, GM ax, M SG), another figure of merit called Maximum Unilateral Transducer Gain (GT U max) is considered.
Definition of MAG is dependent on the value of stability factor K and therefore implemented as a piece-wise function [26]. For K > 1:
M AG = S21 S12 (K −√K2− 1) (4.1)
And for K ≤ 1, MAG is calculated as:
M AG = S21 S12 (4.2)
At the unstable (or conditionally stable) regions of the frequency band and the transition zones around the discontinuities, value of MAG may give misleading information about device performance. Whereas GT U max is independent of device
stability and is a continuous function which helps to determine trends in the device performances more accurately.
Setting the |S12| = 0 in the transducer gain equation [27], we obtain the
unilateral transducer gain:
GT U = 1 − |ΓS|2 |1 − S11ΓS|2 |S21|2 1 − |ΓL|2 |1 − S22ΓL|2 (4.3)
When the input and output of the device is conjugate matched simultaneously for maximum gain, ΓS = S11∗ and ΓL= S22∗ , maximum unilateral transducer gain
GT U max = 1 1 − |S11|2 |S21|2 1 1 − |S22|2 (4.4)
Although this gain definition is based on the unilaterality assumption of the two-port network and gives only an approximate estimation, it is used here for comparing the relative performances of different devices.
4.1.1
Layout Design/Comparison/Selection
Total gate periphery of the device directly controls the amount of current passing from the drain-source channel, hence the maximum power output of the device. However as the electrical length of the device increases, gain drops significantly. This may be attributed to the amplitude and phase imbalance among gate fingers, as well as the growing effects of parasitics in higher frequencies. Fig. 4.2 shows the average GT U max values calculated from many HEMT S-parameter measurements
of various gate peripheries.
Figure 4.2: Relation between total gate periphery and small-signal performance For a given total gate periphery, there is an optimal balance between the length of the transistor, which is determined by the number of gate fingers and the length of individual drain and source contacts; and the gate width of the transistor. For
devices with 1 mm total gate periphery, 4 different layouts seen in the Fig. 4.3 are compared.
(a) 4x250 µm (b) 6x167 µm (c) 8x125 µm (d) 10x100 µm
Figure 4.3: Photomask views of 4 HEMTs with 1 mm gate peripheries and dif-ferent finger configurations
It is found that among the 1 mm HEMTs, 8x125 µm finger configuration is at the sweet spot in terms of small signal performance (Table. 4.1).
Gtumax @ 12 GHz (dB) P3dB @ 10 GHz (Watts) Large-Signal Gain @ P3dB @ 10 GHz (dB) Finger Config. 4x250 9.1 3.6 8.8 6x167 10.1 3.6 10.0 8x125 10.7 3.4 10.4 10x100 10.5 3.2 10.1
Table 4.1: GT U max, power and large-signal gain comparison of 1 mm HEMTs with
different finger configurations
Transistor layout parameters mentioned in this section are marked on the SEM image of a 8x125µm HEMT in Fig. 4.4.
Channel length (or drain-to-source (DS) distance) of the transistor also plays an important role both in small-signal and large-signal performance of the device. While a smaller DS distance contribute to gain and power performance of the de-vice, below certain values may be problematic from fabrication and reliability perspective and may result in premature breakdown of transistor under high RF and thermal stress. When all other parameters kept constant, drain-to-source
Figure 4.4: Transistor layout parameters as marked on the SEM image are: a) gate width, b) drain contact length, c) source contact length and d) drain-to-source distance or channel length
distance (DS) is swept from 3 µm to 5 µm. Small-signal and large-signal perfor-mances of DS3 type devices have found to be better (Table 4.2) as expected, and no reliability problems have been observed with these devices.
There is also a trade-off regarding the drain and source contact lengths. When they are shorter, overall device becomes more compact, thus small-signal gain increases. As we see in the Table 4.2, variants with 18 µm drain and source contact lengths are the ones with highest GT U max.
However compact device length also means that gate fingers are stacked more tightly, which leads to higher channel temperatures under large-signal operation. Transistors with the best small-signal performance therefore, may not be the ideal option for high power and/or high base temperature regime.
Gtumax @12 GHz (dB) Channel Length 3 um 3.5 um 4 um 5 um Drain & Source Contact Variants D18 S18 10.8 10.7 10.6 -D25 S32 10.7 10.4 10.4 10.1 D32 S32 10.6 10.1 10.1 9.9 D32 S54 10.1 - 9.8 9.6 D40 S40 10.0 9.8 9.7
-Table 4.2: GT U max comparison of transistors @12 GHz with various drain &
source contact lengths versus channel lengths
To compare large-signal performances of different layouts, a set of pulsed load-pull measurements at two different chuck temperatures (25◦C and 110◦C) have been performed on these devices with 28V drain voltage. When the drain and source contact lengths are swept while keeping other variables constant, results in the Table 4.3 are obtained.
Load-pull results @10 GHz 25 C 110 C Power Gain (dB) P3dB (Watts) Power Gain (dB) P3dB (Watts) Drain & Source Contact Variants D18 S18 12.3 5.0 11.0 4.0 D25 S32 11.6 5.5 10.1 4.8 D32 S32 11.4 5.6 10.3 4.8 D32 S54 10.3 6.0 10.0 4.9 D40 S40 11.2 5.6 10.1 4.7
Table 4.3: Load-pull results (at 10 GHz) of different contact length variants are compared at 25◦C and 110◦C base temperatures
It becomes apparent that smallest variant with 18 µm drain and source con-tact lengths (D18 S18 ) performs poorly under large signal in both temperature conditions. Gain and power density relation is as expected in 25◦C measure-ments; as the size shrinks, gain increases and power decreases and vice versa. However measurements at 110◦C show that performance of all transistors ex-cept the smallest D18 S18 variant converges, indicating that elevated base plate temperature is the limiting factor for the channel temperature in these variants rather than the power dissipation in the channels. Based on these observations, DS3 D25 S32 variant with 3 µm drain-to-source distance, 25 µm drain and 32 µm source contact lengths has been chosen as the transistor layout.
4.1.2
Parametric Gate Study
Transistor gate structure is one of the most critical elements defining overall performance by determining the small-signal gain and power capability of device. It has been shown that by controlling the gate geometry, it is possible to modulate the electric field in the channel and modify numerous device characteristics [28– 33]. Figure. 4.5 shows multi level gate structure consisting of gate foot, gate head (a.k.a. gate field plate), source connected field plate (SCFP) and corresponding surface electric field intensity graphs across the source-drain channel.
Figure 4.5: Geometry of gate structures and corresponding surface electric field intensities
In the simple gate configuration (with only gate foot), most of the voltage drop between the gain and source occurs at the single large electric field peak concentrated at the drain side of the gate. Addition of a gate head (a.k.a. T-gate or Γ-T-gate) reduces the maximum field strength by adding another peak at the drain end of the gate structure. Finally, utilizing an overhanging field plate electrically connected to the source of the device (which sits at 0 Volts potential) creates a third peak and more evenly distributes the surface electric field.
Gate design affects many physical properties such as to-drain and gate-to-source capacitances, breakdown voltages. Gate fabrication process has also a role in surface trap related effects such as current collapse, which may degrade large-signal performance of the device. Therefore, gate process and gate geometry require careful optimization.
In order to find the optimum gate structure for X-band applications, a para-metric gate study has been performed in the HEMT development photomask. Three parameters of the gate geometry (length of the gate foot, gate head and field plate overhang) are swept across a range of values.
VNA based load-pull measurement results are processed with the help of a MATLAB code that scans all possible source and load impedance pairs to find maximum gain and output power at a given compression value. Load-pull measurements are done with a single fixed source impedance and a number of load impedance points that cover areas of interest in the Smith Chart. Source impedance space is then spanned for every load impedance point using a virtual source-pull method [34] to calculate device performances corresponding to every load-source impedance pair.
Table 4.4 presents the results of gate types without SCFP structures. Keeping the distance between source contact and the gate metal constant, lengths of the gate heads are swept from 400 nm to 800 nm and the gate feet are fabricated at 200 nm, 250 nm and 300 nm lengths. Load-pull measurement results for transistor gains and output powers at 10 GHz under 3 dB compression are compared in the Table 4.4 below.
To improve transistor large-signal performances, source connected field plate structures with various geometries are tested. A similar parametric study has been performed with gate types with SCFP structures, where both gate feet and gate head lengths are swept parametrically. Table 4.5 presents the results of gate types with SCFP structures. Keeping the distance between source contact and the gate metal constant, lengths of the gate heads are swept from 400 nm to 800 nm and the gate feet are fabricated at 200 nm, 250 nm and 300 nm lengths.
Gate Foot Length (nm) 200 250 300 Power Gain (dB) P3dB (dBm) Power Gain (dB) P3dB (dBm) Power Gain (dB) P3dB (dBm) Gate Head Length (nm) 400 10.2 36.6 - - - -500 11.4 37.0 11.7 36.8 10.9 36.4 600 11.3 37.0 11.6 36.9 11.6 36.6 700 10.9 36.8 11.3 36.7 11.1 36.9 800 - - 10.8 36.4 -
-Table 4.4: Output power and large-signal gain comparison of transistors at 3 dB compression at 10 GHz, for gate geometries without SCFP structures
SCFP overhang distances are also kept constant at 375 nm in this comparison. Load-pull measurement results for transistor gains and output powers at 10 GHz under 3 dB compression are compared in the Table 4.5 below.
Gate Foot Length (nm)
200 250 300 Power Gain (dB) P3dB (dBm) Power Gain (dB) P3dB (dBm) Power Gain (dB) P3dB (dBm) Gate Head Length (nm) 400 11.6 36.9 - - - -500 12.0 37.4 12.6 36.8 12.3 36.6 600 11.7 37.3 12.7 36.9 12.6 36.8 700 12.1 37.0 12.4 36.9 12.5 36.9 800 - - 11.9 36.7 -
-Table 4.5: Large-signal performance comparison of gate geometries with SCFP structures at 10 GHz
Load-pull measurement results (@ 10 GHz) of the gate type with the best power density (200 nm gate foot and 500 nm gate head variant with 375 nm SCFP overhang distance) is presented in Fig. 4.6.
37.4 dBm P3dB is obtained at maximum power match and a GT of 12.3 dB
was achieved with maximum gain match at 10 GHz with this gate geometry (Fig. 4.6). Also a simultaneous 12.0 dB transducer gain, 37.4 dBm output power and %52.8 drain efficiency is obtained at (3.0+5.9i)Ω source and (26.2+16.8i) Ω load impedances.
Figure 4.6: GT (green) and P3dB (red) load-pull contours (@ 10 GHz) of the
HEMT type with the best power density at 3 dB compression
Load-pull measurements of various gate types reveal that other similar gate geometries yield comparable results with trade-offs between GT and P3dB. In
Fig. 4.7, load-pull contours of the HEMT type (250 nm gate foot and 600 nm gate head variant with 375 nm SCFP overhang distance) with slightly lower output power and better transducer gain are given.
Figure 4.7: GT (green) and P3dB (red) load-pull contours (@ 10 GHz) of the
HEMT type with better large-signal gain at 3 dB compression
36.9 dBm P3dB is obtained at maximum power match and a GT of 12.84 dB
transducer gain and %56.4 drain efficiency is obtained at (2.7+4.4i)Ω source and (18.4+24.0i)Ω load impedances.
4.2
Topology Selection
Targeted performance goals of for this PA design is given in table 4.6. Specifications Minimum Typical Maximum Operation Frequency Band 8.5 GHz - 11 GHz
Small-Signal Gain 23 dB - -Pulsed Mode Output Power - 41.5 dBm
-PAE 30 -
-Gain Compression - - 6 dB Table 4.6: Design specifications of the power amplifier
Single transistor performances of a 8x125µm HEMT that this design based on are given in the table below.
Frequency 8.5 GHz 10 GHz 11 GHz P3dB (dBm) 34.3 34.9 34.7 Large-Signal Gain (dB) 14.7 13.1 12.1
Table 4.7: Power output and gain of the 8x125µm HEMT (at 3 dB compression) used in design
Note that these results are different from the ones presented in transistor optimization section. This is due to the fact that at the beginning of design, transistor optimization was still in progress, thus the final optimized transistor results were unavailable in the design phase. Hereafter, all presented transistor results will refer to the ones that the design is based on, unless stated otherwise. To achieve the small-signal goal of 23 dB, a 2 stage design is necessary. Out-put power target of 41.5 dBm also dictates at least 4 transistors in parallel are
required at the output stage. For the driver stage, it is possible to employ a single transistor, resulting in a power drive ratio of 1:4. However, driver stage in this configuration may be driven to too much compression, affecting the maximum compression budget for the output stage. On the other hand, using 2 transistors at the driver stage helps with the overall gain compression of the amplifier at the cost of efficiency, as 1:2 power drive ratio will not compress the driver stage significantly. Therefore, these two possible topologies are investigated in more detail with MMIC power simulations.
MMIC power simulations are performed in MATLAB environment, using our own tool developed to process raw data of Vector Network Analyzer (VNA) based transistor load-pull measurements. This MMIC simulation tool applies curve fit-ting on the load plane to interpolate between the measured load-pull data points. Also a virtual source pull technique dubbed ”magic source pull” is implemented to characterize device behaviour for all source impedance space [34]. Tool takes the amplifier topology, matching network losses and impedances presented to transistors as its inputs, and generates power sweep simulations for the overall MMIC and individual amplifier stages. Power simulation of the MMIC with 2:4 topology at 10 GHz is presented in Fig. 4.8 and power sweep simulations of 1st and 2nd stages can be seen in Fig. 4.9a and Fig. 4.9b.
-15 -10 -5 0 5 10 15 20 25 PIN Available (dBm) 20 21 22 23 24 25 26 27 Gain (dB) 10 15 20 25 30 35 40 45 Pout
(dBm), Drain Efficiency, PAE (%)
Gain Pout DEFF PAE Pin (dBm) Pin1 Pout1 Pin2 Pout2 Pout(dBm) Pout(w) Gt (dB) DEff (%) PAE (%) Comp1 Comp2 Comp(dB) Iout1 Iout2 Iout(A) Res 20.75 16.58 30.41 26.43 35.95 41.63 14.55 20.88 30.66 30.41 1.32 4.6 5.92 0.33 1.38 1.71
Figure 4.8: Power sweep simulation of 2 stage MMIC with 2:4 topology at 10 GHz
Fig. 4.8 shows that under 5.92 dB gain compression (denoted as Comp (dB)), 1st stage only goes into 1.32 dB compression (Comp1 ), while the output stage gain is compressed by 4.6 dB (Comp2 ). Figure 4.9 shows the accuracy of the
-5 0 5 10 15 20 25 Pin av (dBm) 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 Gain (dB) 0 5 10 15 20 25 30 35 40 45 50
Pout (dBm) - Drain Efficiency/PAE (%)
Stage-1 Fitting
Fit result (Gain) M-6 Zl=32.36+26.95i M-2 Zl=42.21+16.88i Fit result (Pout) Fit result (DEff) Fit result (PAE)
(a) -5 0 5 10 15 20 25 30 Pinav (dBm) 9 10 11 12 13 14 15 Gain (dB) 0 5 10 15 20 25 30 35 40 45
Pout (dBm) - Drain Efficiency/PAE (%)
Stage-2 Fitting
Fit result (Gain) M-5 Zl=26.32+16.71i M-13 Zl=16.43+15.6i Fit result (Pout) Fit result (DEff) Fit result (PAE)
(b)
Figure 4.9: Power sweep fittings for a) 1st and b) 2nd stage transistors and load-pull measurements superposed
curve fitting, in comparison to two neighboring load impedances, which ensures the accuracy of MMIC simulation under given input conditions (source&load impedances and network losses). This topology offers 41.63 dBm output power under 5.92 dB compression, satisfying the design targets.
Alternative 1:4 topology is also simulated in the same way and the results are presented in Fig. 4.10. -15 -10 -5 0 5 10 15 20 25 PIN Available (dBm) 19 20 21 22 23 24 25 26 27 Gain (dB) 10 15 20 25 30 35 40 45 Pout
(dBm), Drain Efficiency, PAE (%)
Gain Pout DEFF PAE Pin (dBm) Pin1 Pout1 Pin2 Pout2 Pout(dBm) Pout(w) Gt (dB) DEff (%) PAE (%) Comp1 Comp2 Comp(dB) Iout1 Iout2 Iout(A) Res 20.75 19.59 32.74 25.55 35.66 41.34 13.61 20.58 32.31 32.02 2 4.01 6.01 0.21 1.3 1.52
Figure 4.10: Power sweep simulation of 2 stage MMIC with 1:4 topology at 10 GHz
Power simulation results of 1:4 topology reveal that despite the boost in ef-ficiency, output power offered by this topology falls just short of design spec-ifications. While this simulation is based on assumptions of load and source
-5 0 5 10 15 20 25 Pinav (dBm) 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 Gain (dB) 0 5 10 15 20 25 30 35 40 45 50
Pout (dBm) - Drain Efficiency/PAE (%)
Stage-1 Fitting
Fit result (Gain) M-6 Zl=32.36+26.95i M-2 Z
l=42.21+16.88i Fit result (Pout) Fit result (DEff) Fit result (PAE)
(a) -5 0 5 10 15 20 25 30 Pinav (dBm) 9 10 11 12 13 14 15 Gain (dB) 0 5 10 15 20 25 30 35 40 45
Pout (dBm) - Drain Efficiency/PAE (%)
Stage-2 Fitting
Fit result (Gain) M-5 Zl=26.32+16.71i M-13 Zl=16.43+15.6i Fit result (Pout) Fit result (DEff) Fit result (PAE)
(b)
Figure 4.11: Power sweep fittings for a) 1st and b) 2nd stage transistors and load-pull measurements superposed
impedances that will be presented to devices as well as assumed matching net-work losses, thus is not definitive; it gives a relative idea about the expected results from the specific topologies.
8.5 9 9.5 10 10.5 11 Frequency (GHz) 5 10 15 20 25 30 35 40 Power Gain(dB), P out (dBm), PAE (%)
Sim. Power Gain Sim. P
out Sim. PAE
Figure 4.12: Power simulation results at 6 dB compression for 2:4 topology in 8.5 GHz - 11 GHz band
Based on this analysis, amplifier design is commenced with 2:4 topology due to its better prospects to deliver specified output power under limited gain compres-sion. Power sweep simulations performed for 2:4 topology at 6 dB compression across the band yield the results presented in Fig. 4.12.
4.3
Passive Component EM Model Library
Behaviour of passive circuit elements substantially deviate from their low fre-quency lumped models as the frefre-quency increases. To simulate high frefre-quency response of on-chip passive elements, either analytical lumped-element equiva-lent circuit models for distributed components have to be developed, or these distributed structures require to be simulated in EM field solvers.
While it is faster and computationally easier to work with analytical lumped-element equivalent circuit models of passive lumped-elements, it is particularly difficult to obtain accurate, broadband and scalable models that hold for wide range of layout parameters. On the other hand, despite its flexibility and better accuracy, performing EM simulations for every layout part causes layout design process to be cumbersome and slow.
To overcome this problem and benefit from the advantages of these two ap-proaches; table based models of microstrip components has been created where parametric layouts of all the circuit components are swept across a range of com-mon parameter values and EM simulated beforehand (Fig. 4.13a).
Simulation results corresponding to these nested sweeps are kept at ADS em-Model tables and recalled when needed (Fig. 4.13b).
(a) Nested parameter sweep schematic of inductor
EM model (b) EM model datatable of the inductor
Any data that falls between the simulated parameter values can be interpo-lated. This is considered to be a better approach than depending on analytical models, since the analytical models are essentially derived from EM analysis by curve fitting them to an equation. Typically, the equation is too simplistic to include all the details at high frequency that the EM simulation can capture.
EM simulation substrate stack (Fig. 4.14) in ADS for the 100µm thick mi-crostrip process is optimized based on the DC and RF measurements of passive test structures and process data.
Figure 4.14: EM substrate stack used in ADS
Conductivities of 1st (thin) metal (MET1 ) and 2nd (thick) metal (em m2 s1 ) layers are 3.4 × 107S/m and 3.7 × 107S/m respectively. Sheet resistance of thin film resistor layer (TFR) is 30Ω/. Metal-insulator-metal (MIM) capacitance density between the 1st and 2nd metal layers is about 258 pF/mm2. Dielectric
loss tangents for capacitor nitride layer (SiN2 ) and Silicon Carbide base layer (SiC2 ) are 0.001 and 0.03 respectively.
To demonstrate the high frequency behaviour of on-chip spiral inductors and the accuracy of the EM models in predicting them; measurement results of a fab-ricated spiral inductor that corresponds to 600 pH (seen in the layout in Fig. 4.15) are compared (in Fig. 4.16) with its EM model and an ideal lumped inductor.
Smith Chart Fig. 4.16b illustrates that spiral inductor quickly deviates from the ideal inductor behaviour as the frequency increases; which is captured by the EM model fairly accurately, together with the increase in effective inductance and the resonance around 38 GHz.
Figure 4.15: Layout of the on-chip spiral inductor that correspond to 600 pH
(a) Effective inductance comparison (b) Frequency response of inductors in
Smith Chart
Figure 4.16: Comparison of inductor measurement and simulation results with ideal inductor response
As for the accuracy of distributed element simulations, measurement and EM model simulation results of a 50µm wide and 1 mm long line (Fig. 4.17a), cor-responding to a 62Ω transmission line of 45◦ electrical length at 12 GHz are presented in Fig. 4.17b.
Fig. 4.17b shows that EM model representation of transmission lines are also fairly accurate up to Ka-band frequencies.
(a) Layout of the microstrip transmission line
(b) Frequency response comparison of mea-sured, modeled and ideal TLs in Smith Chart
Figure 4.17: Comparison of transmission line measurement and simulation results with ideal TL response
4.4
Stability
Preventing unwanted oscillations in amplifiers is a vital aspect of the design cycle. Circuits become more complex from the stability analysis perspective as multiple transistors are used either as cascaded or in parallel configuration; leading to many possible cases that may satisfy oscillation conditions.
Especially in power amplifiers, stability analysis becomes more critical than small-signal amplifiers. Since transistor characteristics change under large-signal regime and pulse operation modes, conventional small-signal stability analysis is not sufficient to ensure unconditional stability of the amplifier [35]. In addition to the standard even-mode tests, necessary precautions against odd-mode and parametric oscillations should also be taken.
In this design, small-signal even-mode stability is ensured by checking the µ factors of individual cascaded stages. Instead of designing stability networks
based on a single S-parameter measurement, multiple S-parameter measurements of the same type of transistor are used to account for different operation&bias conditions, fabrication variations and also to improve stability against parametric oscillations [35].
For odd-mode stability tests, we implement the method proposed by Freitag [36] by calculating impedances and admittances at the inputs and outputs of all active devices for all odd excitation modes to see whether they satisfy oscillation conditions.
To ensure unconditional stability in and out of the band, resistive losses need to be introduced by adding series or shunt stability networks to the circuit. How-ever as the full design develops, loss contribution from these networks can be reduced or these networks can be removed altogether as the losses coming from the practical implementation of the layout help to stabilize the network.
A two step approach is followed in stabilization, where transistors are initially stabilized before matching network design with the addition of a stability unit cell, improving even-mode stability to a certain degree; and then after the full layout design of matching and bias networks are completed, extra stability networks (that don’t affect matching at the operation frequencies) are added to gate bias lines to compliment even-mode stability and provide extra suppression against parametric oscillations of the amplifier stages.
4.4.1
Even-Mode Stability
In the even-mode stability analysis, µ factors of the two port networks are consid-ered, since they better indicate relative level of stability, a larger value meaning greater device stability.
µ = 1 − |S11|
2
|S22− ∆(S11∗ )| + |S21S12|
µ0 = 1 − |S22|
2
|S11− ∆(S22∗ )| + |S21S12|
> 1 (4.6)
where ∆ is defined as:
|∆| = |S11S22− S12S21| (4.7)
Stability (µ factor) and MAG of a single 8x125µm HEMT can be seen in Fig. 4.18.
Figure 4.18: Stability and MAG of a 8x125µm HEMT before stabilization As the first step of even mode stabilization, a parallel RC circuit added in series (Fig. 4.19) just before the transistor gate feed. Resistor and capacitor values of the stability cell are tuned in such a way to impact the MAG in band minimally and improve out-of-band stability (especially in low frequencies) until µ and µ0 are greater than approximately 0.9 throughout the frequency spectrum. Tran-sistors are not unconditionally stabilized at this point, as the loss contribution that will come from realized matching and bias networks will also increase the stability. Layout of this stability cell is implemented symmetrically to create less asymmetry for RF signal propagation between gate fingers.
A single µ factor analysis should be a sufficient indicator of unconditional stability for all passive loads presented to a two port network under nominal small-signal conditions. However, stability behaviour of transistors change under different bias (different voltages and quiescent drain currents, CW vs. pulsed operation) and temperature conditions. Also, transistors performances vary on a single wafer, as well as among the different fabrication runs. To account for
Figure 4.19: Layout of the transistor with input stability cell
such variations, batch S-parameter simulations encompassing a range of devices and operation conditions are performed for even-mode stability analysis using the Data Access Component (DAC) tool of ADS (Fig. 4.21).
Next step of device stabilization is implemented after the design of matching and bias networks are completed. Even-mode stabilities of individual amplifier stages partitioned as in the Fig. 4.20 are analyzed. Extra stability elements are added to gate bias lines to improve stability until both two port networks are unconditionally stable (Fig. 4.21).
Figure 4.20: Layout partitioning of 1st and 2nd stages in even-mode stability tests
(a) 1st stage µ stability factors (b) 2nd stage µ stability factors
Figure 4.21: Even-mode stability results of both stages
the operation frequency band, since they are added after the RF choke inductors and RF grounding capacitors in the bias lines and remain in the DC portion of the circuit. Overall stability circuit topology is in line with the scheme suggested for suppressing parametric oscillations [35] and is expected to improve stability against unpredicted low frequency oscillations.
4.4.2
Odd-Mode Stability
Amplifier stages where a number of transistors are used in parallel configuration are designed to work in even-mode operation, where all transistors are assumed to be excited with an RF signal of the same phase and amplitude. However transistors can have slight variations in gm and gate threshold voltages which,
when biased with the same gate voltage, results in different quiescent drain cur-rents between transistors. In addition to that, in the realized layout, individual matching networks of each transistor will present slightly different load and source impedances. These differences in transistor performances may create conditions for odd-mode or differential-mode excitations. Combined with high transistor gain and finite device isolation (reverse transmission), these conditions may lead to odd-mode oscillations through the feedback loops existing between parallel transistors. Therefore, amplifier designs consisting of multiple parallel transis-tors have to be checked for odd-mode stability using appropriate techniques.
