Analog integrated circuit of a low level high voltage current source with capacitive load compensation

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CAPACmVE

LOAD

COMPENSATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL AND

ELECTRONICS ENGINEERING

AND THE INSTITUTE OF ENGINEERING AND SCIENCES

OF BILKENT UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

MASTER OF SCIENCE

Mustafa Ertugrul ÖNER

Octqber,i&97

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ANALOG INTEGRATED CIRCUIT OF A LOW

LEVEL HIGH VOLTAGE CURRENT SOURCE WITH

CAPACITIVE LOAD COMPENSATION

A THESIS

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

AND THE INSTITUTE OF ENGINEERING AND SCIENCES OF BILKENT UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF SCIENCE

By

Mustafa Ertugrul Oner

October 1997

'j

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э . .

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I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a thesis for the degree of Master of Science.

Prof. Abdullah Atalar(Supervisor)

Assistant. Prof. Dr. Orhcin Aytiir

Assistant Prof. Dr. Mehdi Fcirdmanesh

Approved for the Institute of Engineering and Sciences:

Prof. Dr. Mejyaiet Baray

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ABSTRACT

ANALOG INTEGRATED CIRCUIT OF A LOW LEVEL

HIGH VOLTAGE CURRENT SOURCE WITH CAPACITIVE

LOAD COMPENSATION

Mustafa Ertiigrul Öner

M.S. in Electrical and Electronics Engineering

Supervisor: Prof. Dr. Abdullah Atalar

October 1997

Atomic Force Microscopes(AFM) are used to sense the deflections on the crys talline surfaces and convert the information gathered to an image of surface map. In a newly proposed interferometric sensor, cantilevers are micromachined into the shape of interdigitated fingers to form a diffraction grating and the tip displacement is determined by measuring the intensity of diffracted modes. Detection of modes is achieved by means of a photodetector(PD) array mounted just above the cantilevers. For this purpose , a PD array of 2 x 8 composed of MSM-PDs is designed and manufactured. A p'*'/n PD is also designed for testing. In addition, a high voltage low level current source is required to drive the tips of the cantilevers for the purpose of lithography. The current source designed for this purpose can supply lOnA current through the resistive cantilever in spite of an existing capacitance at load. Current source includes an internal capacitive current compensation circuit to fix the current of resistive load at lOnA. Test of designed circuit is done and prototypes of chip are fabricated using Alcatel Mietec I2T CMOS process. PD array and current source are supposed to be prototypes of the related blocks in AFM.

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ÖZET

y ü k t e k i k o n d a n s a t ö r a k im in i t e l a f i

EDEBİLEN

DÜŞÜK SEVİYE YÜKSEK GERİLİM AKIM KAYNAĞI

TASARIMI

Mustafa Ertıığrul Öner

Elektrik ve Elektronik Mühendisliği Bölümü Yüksek Lisans

Tez Yöneticisi: Prof. Dr. Abdullah Atalar

Ekim 1997

Atomik mikroskop, kristallerin 3Üzey haritalarını elde etmekte kullanılır. Kristallerin yüzey sapmaları mekanik ve optik bir takım düzenekler vasıtasıyla elde edilir ve bu bilgi daha sonra görüntüye dönüştürülür. Yüzey sapmalarını ölçmek için kullanılan ızgaralar lazer ile aydınlatıldığında sapmanın büyüklüğü ile orantılı yoğunlukta ışık modları elde edilir. Bu modları ölçmek için MSM fo- todiyot dizgisi içeren bir çip tasarlandı. MSM fotodiyotlar CMOS teknolojisine gösterdikleri uj'umdan dolayı seçildi.

Buna ek olarak, ızgaraları sürmek için gereken lOnA’lik akim kaynağı hazırlandı. Akım kaynaği birbirine parallel direnç ve kondansatörden oluşan bir yükü sürebilecek ve direnci içeren koldan lOnA’lik akım geçirebilecek şekilde tasarlandı. Kondansatör içeren kolda yük gerilimindeki değişiklerden dolayı oluşan akım, akım kaynağı içerisinde yapılan düzenlemeler ile telafi edildi. Yüksek gerilim akım kaynağının çipi yapıldı.

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ACKNOWLEDGEiMENT

I would like to express my gratefulness to Prof. Dr. Abdullah Atalar for his suggestions and guidance throughout the development of this thesis.

I wish to thank A.Suat Ekinci for his invaluable help.

I sinceiely thank to Kahraman Güçlü Köprülü and Tolga Kartaloğlu for thoür helps in optical measurements.

Special thanks to Suzan and my parents for their encouragement and pa tience.

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LIST OF FIGURES

1.1 Cantilever on Crystal S u r f a c e ... 2 1.2 Current of e-beam resist vs. substrate v o lta g e ... 3

2.1 N-type and P-type current mirror b lo c k s ... 6 2.2 Cascaded current mirrors for current amplification and attenuation 8 2.3 Simple Model for Current S o u r c e ... 11 2.4 lOnA Current Source with no load capacitive current compensation 12 2..5 Final lOnA Current Source with no load capacitive current com

pensation ... 13 2.6 Voltage Divider Bias Chain 16 2.7 Available Bias V oltages... 17

3.1 A simple model of current s o u r c e ... 19 3.2 (a) Plot of Output Impedance (dB) vs. Frequency (Hz-log) and

(b) Plot of Output Current (A) vs. Vo (V) ... 20 3.3 Current Source Driving Variable Resistive L o a d ... 22

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3.4 (a): R1 vs. Time (s) (b); Output Current vs. Time (s), (c): Output Current vs. Time (s)-zoomed o u t ... 22 3.5 Current Source Driving Variable Resistive Load and a Parallel

Capacitance ... 23 3.6 (a): Current through resistive branch vs. Time (s) (b): Current

through capacitive branch vs. Time (s) (c): Total current of source vs. Time ( s ) ... 24

4.1 D ifferen tiato r... 26 4.2 Differentiator connected to the current s o u r c e ... 26 4.3 Capacitive currents when differentiator connected, (a); Load

resistance vs. Time (s), (b): Load capacitive current vs. Time (s), (c): Capacitive current due to differentiator vs. Time (s) . . 27 4.4 NMOS and PMOS Output Buffers 28 4.5 NMOS Buffer DC-Level Shift Operation ... 29 4.6 NMOS Buffer DC-Level Shift vs Vin ( V ) ... 30 4.7 (a); Small Signal Voltage Gain and (b): Phase S h if t... 32 4.8 Differentiator and Buffer connected to the current source . . . . 33 4.9 (a): Load Impedance vs. Time (s), (b): Current Through Load

Capacitance, (c); Differentiator Output , (d): Current Through Load R esistance... 34 4.10 Voltage Controlled Current Source 36 4.11 Non-inverting Amplifier with High Input Im pedance... 38 4.12 Overall Circuit with Capacitive Current C o m p en satio n ... 40 4.13 Current through resistive load after current compensation . . . . 41

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4.14 Resistive load currents with and without com pensation... 42

4.15 Resistive load currents with and without compensation-Effect of feedback g a i n ... 43

4.16 Feedback Control Model of Compensated Current Source . . . . 45

4.17 Root-Locus A n a ly s is ... 46

4.18 Open-loop gain of current source, (a) Gain (dB) vs. Freq (b) Phase vs. Freq - Feedback Gain(K)=1.3 ... 47

4.19 Open-loop gain of current source, (a) Gain (dB) vs. Freq (b) Phase vs. Freq - Feedback G ain(K )=3.47... 48

5.1 Operational Amplifier ... 54

5.2 Determination of Open-Loop Gain ... 55

5.3 Open-Loop Gain (dB) vs. Frequency ( H z ) ... 56

5.4 Determination of Phase Margin ; (a): Open-loop gain (dB) vs. Freq.(MHz), (b): Phase vs. Freq. ( M H z )... 57

5.5 Determination of Offset V o ltag e... 58

5.6 Output Impedance vs. Frequency[10Hz-10MHz]... 58

5.7 (a) Differential Mode Gain (dB), (b) Common Mode Gain (dB), (c) CMRR ( d B ) ... 59

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6.2 Responsivity (A/W) versus Wavelength (/¿m). EiTect of higher and lower wavelengths... g5

6.3 p + /n Photodetector ... 66

6.4 n + /p Photodetector ... 67

6.5 Structure of Basic M S M -P D ... 67

6.6 Cross-section of M S M -P D ... 68

6.7 I-V characteristics of an MSM-PD under different light powers. . 69

6.8 Finger Width dependece of Quantum Efficiency and Capacitance 70 6.9 Experiment Setup for Performance Measurement of P D ... 71

6.10 Layout dimensions of p+/n photodetector... 72

6.11 Impulse Response for Incident Power of 465nW and Rj = lOA/fi 73 6.12 Impulse Response for Incident Power of 397niy and R j = lOMU 74 A.l Layout of 18kfl R e s is to r ... 80

A.2 Layout of Voltage Divider Bias Chain 81 A.3 Layout of NMOS Buffer 82 A.4 Layout of a Single Bonding P a d ... 82

A.5 Layout of Uncompensated Current S o u r c e ... 83

A.6 Layout of High Voltage Operational A m p lifier... 84

A.7 Layout of Compensated Overall Current S o u r c e ... 85

A.8 Layout of Compensated Overall Current Source With Bonding P a d s ... 86

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B.l Layout of a Single p + /n PD . . . .

B. 2 Layout of a Single MSM-PD ₈₈ B.3 Layout of MSM-PD array ₈₉ B.4 Layout of and n ^ /p photodetector arrays ₉₀

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LIST OF TABLES

2.1 Transistor sizes of lOnA Current Source... 14 2.2 Transistor sizes of Voltage Divider Bias Chain... 18

4.1 Open Loop Gains and Phase Margins. 51

5.1 Transistor sizes of Operational Amplifier... 60

6.1 Absorption Coefficient of Silicon for Different Wavelengths. . . . 72 6.2 Responsivity and Quantum Efficiency calculations for R j = 4.7k

and Ao = 633nm ... 73

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C h ap ter 1

In tro d u ctio n

Atomic Force Microscopes (AFM) are devices used commonly to get an image of crystalline surfaces on the atomic level. AFM’s are able to measure deflec tions that are much less than 1 Â. The cantilever with an integrated tip is the main element of those microscopes. Design of cantilevers is an important topic because it determines the sensitivity of the system.

The measure of deflections on atomic level is achieved by means of tech niques such as tunneling [1], the optical lever [2], interferometer [3] and piezoresistor [4]. Optical techniques become more and more popular because of their high sensitivity. Schonenberger and Alvarado [5] developed a scheme in which a biréfringent prism is used to divide a laser into sensing and ref erence beam. The prism is placed so that the reference beam is reflected off the cantilever and sensing beam is reflected near the tip. Reflected beams are detected and analyzed by a split photodiode. Rugar et al. [3] developed a deflection sensor based on the interference of light between cleaved end of an optical fiber and the backside of cantilever.

A new interferometric sensor for the AFM where a cantilever is micromachined into the shape of interdigitated fingers to form a diffraction grating is proposed by A.Atalar [6]. This technique requires an illumination source and a standard photodetector. A resolution comparable to other interferometric

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sensors can be achieved. In that method, intensity rather than the position of the reflected beam is measured and therefore the problem of aligning an array of photodiodes is eliminated.

When the cantilever is illuminated by a Gaussian beam with diameter of 20/x and a wavelength of A = 670nm, the fingers form a phase sensitive diffraction grating and the tip displacement is determined by measuring the intensity of diffracted modes. As deflection increases, the intensity of the reflected beam at mode diminishes and at mode rises. For a deflection of a quarter wavelength , reflected beam at mode is minimum and it is maximum at

mode. The cantilever deflection can be determined by either measuring the intensity of the mode, mode or difference between the modes. To detect

lOnA Current Source

Figure 1.1: Cantilever on Crystal Surface

the intensity of deflected modes, an array of photodetectors placed just above the cantilever tips is required. Metal-Semiconductor-Metal photodetectors are used for this purpose. MSM-PD’s have attracted significant interest recently for device applications due to their wide bandwidth, low capacitance, low cost of fabrication, high sensitivity, low dark current and monolithic integrability with high speed electronic and microwave devices [7]. An MSM photodetector array is prepared to meгtóure the intensity of diffracted modes.

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The cantilever tips must be driven by an high voltage low level current source for the purpose of lithography [8]. In order to get surface map of crystalls, the substrate surface is first covered by e-beam resist. The scanning tip of the micromachined cantilever expose the e-beam resist by supplying a curent of lOnA as shown in Figure 1.1.

The exposed regions of e-beam resist are developed afterwards by some chemical processes and image information is obtained. The exposure of the e-beam resist could also be achieved by means of a fixed voltage supply. But it is observed that the change in substrate voltage from 40V to 80V make the constant exposure impossible. Figure in 1.2 shows the current of e-beam resist

V substrate 40V...80V

Figure 1.2: Current of e-beam resist vs. substrate voltage

vs. substrate voltage. It is evident from above plot that if cantilever tips are driven by a fixed voltage source then the amount of current through the e-beam resist will change drastically due to varying ON time and constant exposure could not be achieved. The proposed constant current source overcomes this problem and provide constant exposure [9]. The typical level of current is lOnA and required voltage is —lOOV.

In actual scan of cantilever tips over crystalline surfaces, an inherent ca pacitance of order 1 — 2pF will also be present. The current source must have the ability of supplying lOnA current through the resistive cantilever load in spite of the existing capacitance. The resistive load is time varying and is

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around 3 — 8GÎÎ which cause the load capacitance to supply or withdraw cur rent through the resistive branch. lOnA current source must include an internal load capacitive current compensation circuit to fix the current of resistive can tilever load at lOnA.

This thesis includes the design of Load Capacitive Current Compansating Current Source and a Metal-Semiconductor-Metal Photodetector Array, two of the building blocks of AFM.

In Chapter 2, the elements of CMOS High Voltage lOnA Current Source W ithout Capacitive Current Compensation is presented. A brief discussion on current mirror stages, current amplification and de-amplification , cascode out put stages and voltage divider bias circuits is given. The transistor dimensions are calculated for lOiiA current source.

In Chapter 3, the performance of the fixed lOnA current source is analyzed. Its output current stability against the changes in output voltage is observed. Simulations for both cases: resistive load only and resistive & capacitive loads are presented.

In Chapter 4, the capacitive current compensating circuit is introduced. The building blocks of that circuit, namely differentiator, buffer, voltage con trolled current source and non-inverting amplifier are discussed. Their per formance tests are presented. The overall circuit of Low-Level High-Voltage Current Source with Capacitive Load Compensation is given.

In Chapter 5, the operational amplifier which is used in the current source is introduced. Its performance tests on open-loop gain, phase margin, output impedance, CMRR etc. are presented. Transistor values used in design of op amp is given.

In Chapter 6, MSM photodetector structures and their capabilities are dis cussed.Test results of jn photodiode are given.

In Appendix A, layout of current source building blocks are presented. Overall circuit layout is also added. In Appendix B, photodetector layouts are given. Appendix C inludes the process parameters of transistors. Appendix D shows pin configuration of current source chip.

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C h a p ter 2

C urrent Su p p ly B u ild in g B locks

2.1 Current Mirror

2.1.1 In trod u ction

One of the main blocks of the current compensated lOnA current source is the current mirror. There exists many realizations of current mirrors serving for various needs. They might be used to copy a current from any circuit branch. Parallel connection provide the opportunity of generating many exact copies simultaneously. In addition to that, successive connection of complementary current sources allows changing the direction of current.

Figure 2.1 shows simple n-type and p-type current mirror blocks. The n-type block is used for withdrawing current from output node while p-type is used for supplying current.

hias represent the current to be mirrored with a certain gain. By connecting

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governing equation of transistor current in saturation region is: h ia a — 2*^^ ( ^ ) i( Kj51 “ + ^ VdSi) (2.1) Vdd

A

Vdd

A

Vgsl=Vgs2 Ml M2 libias lo Vload Vss

Figure 2.1: N-type and P-type current mirror blocks

Bias current enforces gate-to-source voltage of Mi and M2 to reach a certain value. Assuming M2 also in saturation, the same bias current will flow through the drain of M2, provided Mi and M2 are same size transistors. If the size of the transistors are different, drain current of M2 will change in proportion to

{W/L) ratios of Ml and M2. The value of Vgs\ is determined by [W¡ L) ratio

of first transistor. If the output voltage of current source is a low value, then it would be better to set gate-to-source voltage as low as possible to make M2 enter saturation more easily.

O utput current /0 set by M2 is given to be:

_ [‘■n (_)2(I/(552 — Vr„)^(l + AVi)S2) (2.2)

Equations 2.1 and 2.2 yield

A .

Ibxas

{W!L)2 (1 + Wdst)

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If there exist no loading effect on output transistor M2, drain to source voltages Vpsi and Vds2 would become equal. Even if this is not true, very

small values of channel-length-modulation parameter A guarantees that: (1 -|- XVusi)

(1 + AI/d si) 1

Then we can safely use current mirror gain equation:

{W IL)2

Iq — Jbia

(W/L),

(2.4)

(2.5)

If we call current gain factor to be /3, then:

( W / L)2

C r / i ) , (2.6) and

Iq = l3Ibi, (2.7)

2,1.2

C urrent A m p lific a tio n /A tte n u a tio n

Appropriately choosing the gain factor /?, current amplification and attenuation can be achieved. Successive use of mirror blocks for this purpose are shown in Figure 2.2. Let’s call: ( W / L U {W /L )n Pi ~ 777777V") P2 “ (W/L)la (WjL) .,|8n = 2a { W I L U {WlL)na

(

2

.

8

)

The bias current mirrored through each current mirror block with a certain gain. When current reach to the last stage:

h — P3P2P1 h i (2.9)

If n of those mirror blocks are cascaded:

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Mia

o — ' + 1— o 0 — 1 + ^— o

V g s l _{V gs3}

V ’ ' f ■ 1

Vss Vss Vss Vss

Figure 2.2: Cascaded current mirrors for current amplification and attenuation

If multiplication of ^ ,’s is greater than one, cascaded mirror stage functions as a current amplifier and vice versa.

2.1.3 S atu ration C ondition

In cascaded use of current mirrors, one must be careful in keeping the tran sistors A/,t in saturation. Actually, if the current gain of each mirror block is grater than one, then there exist an upper bound for the bias current in terms of supply voltages and mirror gains. This upper bound constraint weakens in current attenuation but still exist.

For the sake of convinience, let:

¡inCox.W Ki =

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Then

I a (2.12)

From Equation 2.1

Vis. = i / # i + Kr„

I<u

The drain current of Mu becomes

h =

(2.13) (2.14) and enforce Vqs2 to be \/ I ^^Ib/I^la^btas , ,, yasi - \ l --- --- + Vi

K,

7a T p (2.15)

To get Mib in saturation we must have

^DSlb ^ Fg51 ~ Vxn _(2.16)

but also

Vosib = Vdd — V s s — 1147521 _(2.17)

Combining equations 2.15, 2.16 and 2.17

Ku

K l a (2.18) or ^bias ^ 7^1 a [VpD — Vss — Vt 1 + ^ { K [ b l K2a) Pi 2 (2.19)

Above statement gives the condition of keeping Mu in saturation. We will follow a similar procedure to find the saturation condition of M u’s. To make M26 enter into saturation

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If we assume |Vrp| = Vr„ = Vj referring to process parameters given in Appendix C then

\Vasz\ = J ~

‘% />,.. +14-

( 2 .21)

Substituting Equation 2.21 into 2.20 and using |V'd526| = Vod ~ Vss - Vgsz

hoD ~ 1^55 ~ ll'fessi ^ |VgS2| ~ (2.22)

or

VoD — ^SS — Vt — lUbKn -^bias d. \ l, ^ ¡ K n K n r---hia

K\aK2aKza K l a

(2.23)

Then the upper bound on Ibias is found to be:

KxaKza r ^ D D ~ VsS ~ -,2

^btas ^ (2.24)

We may generalize this result to n-mirror blocks. To keep M„6 in saturation, upper bound on hiaa is as follows:

K l J < 2 a K 3 a ' ' ' I<n

^bias ^ r/· V

dd — Vss - Vt ,2

K n K2bKzb · · · /V(„_1)6 1 + y(/T.,//r(„+i)J

Using Equations 2.12 and 2.25

^bias ^

K.

Vdd — Vss — Vt

n := l' 1 + xJ{Kna/I<in+X)a)

(2.25)

(2.26)

The saturation condition of the last transistor of cascaded stages depends mainly on the output node voltage. If this voltage is high in magnitude com pared to the available supply voltages, it would be difficult to keep output transistor in saturation.

Saturation of M,¡,’s will not be a direct problem because we will use cascaded current mirror stages for current de-amplification by setting ^ < I . However the saturation condition have to be kept in mind for a proper design.

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2.2 lOnA Current Source

The main difficulty of the design of the lOnA current source is the lOOV supply range. Actually, we are required to design the current source using -f5V and —95V as supply voltages. This current source will drive the cantilevers in AFM and the supply voltages are chosen for this requirement.

The operation of the current source is limited by supply voltages. Voltage swing at output node Vo cannot exceed available supply range, otherwise some of the transistors in current source cuts off and operation fails. Also the output impedance Ro of the current source must be chosen as high as possible in order to get rid of changes in supply current of lOn.A when output voltage sweeps a certain voltage range.

.A lOOV voltage drop accross the current source with 10j?A requires lOOV

lOnA = 10^Π (2.27) resistance which is impractical in chip fabrication process. This much of re sistance cannot be obtained directly and therefore we must propose another method. We will first start from a relatively higher current level around a few micro ampers and use cascade current mirror stage for current attenua tion down to lOnA. One must be careful in choosing starting current level. At high levels of currents, power consumption comes into play. If overall lOnA

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current source withdraws a current of 10mA, this will correspond to IVF power consumption. Keeping this fact in mind, we will try to use currents as low as possible.

V Vss V V s s

Figure 2.4: lOnA Current Source with no load capacitive current compensation Circuit in Figure 2.4 shows the general topology of the lOnA current source. Supply voltages used are Vdd ~ oV and V$s = —95V'. The transistor A/j in

subcircuit Cl supplies the current /¡„ai, which make all the transistors ON.

Vbias is the bias voltage which is supplied by another voltage divider circuit

discussed next. The gate of the Mi is at almost infinite impedance and will have no loading effect at bias circuit.

Subcircuits C2 and C3 are cascaded current mirror stages and achieve a. current division. They also isolate current biasing transistor Mi from voltage variations at the output node.

Figure 2.5 shows the modified form of uncompensated current source. During capacitive current compensation in Chapter 4, we will design a load capacitive current compensating circuit and generate a copy of load capacitive

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current. Tliis current will be fed back through non-inverting pin of an oper ational amplifier. Non-inverting pin will be connected to the drain of M4 as shown in Figure 4.12. In order not to saturate the operational amplifier, this voltage must be somewhat lower than Vd d- Actually, to achieve a current divi sion, the (Wf L) ratio of transistor M4 cannot be chosen so low, which leads us to gate-to-source voltage of around IV. Therefore, the voltage at the node to which operational amplifier will be connected become around i V . This volt age is very close to Vdd and saturate the operational amplifier. To draw that

voltage down to around OF and give a proper operation range to operational amplifier, two more p-type current mirror stages will be connected in parallel to C3. To achieve output stability, Cascode (or Improved Wilson) current

Vdd

A

V bias o---

_{I C}

Vdd M l M4 M2 M3 V ss Vss Vdd A

- n h r - l L

" • n i —

i

- I

l

□ H - i c :

M9 M7 M6 MIO V Vss Vdd A M12 M il Vss Vdd A M13 M14 M16 V Vss

P l - H r

Xo M15 M17 V Vss

Figure 2.5: Final lOnA Current Source with no load capacitive current com pensation

source is placed at the last stage, labeled as subcircuit C4. {WfL) ratios of

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Transistor (W/L) Ml 40 fi /221 /Í M2 20 /20 n M3 20 fi /20 /Í M4 22 n /20 /Í Ms 22 /Í /20 /i Me 22 /Í /20 ¡1 M7 22 /r /20 /Í Ms 21 /Í /20 /i Mg 21 /i /20 9, Mio 40 /i /24 /Í Mu 20 /Í /80 n Ml 2 40 /Í /24 /Í Mi3 20 /i /80 /Í Mu 50 /i /10 /i M,5 20 ft /50 /i M16 50 /i /10 /t Mir 20 /i /50 /Í

Table 2.1: Transistor sizes of lOnA Current Source.

2.2.1 O u tp u t Current S tab ility

The Cascode Current Source serves as the output stage and prevents the output current from clianging in response to load voltage variations. Cascode Current Source is composed of two current mirror blocks connected in parallel. The small signal output resistance is given to be

Ro — ^07(1 + {gml + 9mb7)l'o9] + ^o9 (2.28) where r . = 9d (2,29) and 9d =

1 + ^Vps

Id-

(2.30)

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Also the transconductance g ,n b is given to be

9mb

+ VsB (2.31)

The low channel-length modulation characteristics of the process causes' Rq

to reach even 10^Π by which we achieve good output current stability. Actually

R o =

Av;

A h

Ah =

Ro (2.32)

and the relation in Equation 2.32 tells us that to get a few pico ampers change in output current in response to possible 30V to 80V change in load voltage we require an output impedance of order many giga ohms. Cascading more and more current mirror blocks will continuously raise output impedance and output current stability, but this time it will have a negative effect on possible range of output voltage swing to keep output transistors in saturation. In other words, maximum load impedance that current source can drive fall below the maximum possible value of lOGTi for supply range of lOOV and current of lOnA.

2.3 Voltage Divider Bias Circuit

-Amplifier stages and current sources need various dc bias voltages and currents for their operations. Usually the circuits have only two dc voltage supplies ,

Vdd > 0 and Vss < 0, and all other bias voltages must be obtained externally.

To obtain the dc bias voltages H i, H 2, · · · > Hn where U55 < Vti < H 2 < · · · < Hn < Vd d, I have used voltage division. It is not suitable to use resistive

dividers in MOS technology because of their large silicon area consumption. Instead, MOSFETs are used in a totem-pole configuration [14] .

Figure 2.6 shows the PMOS Voltage Divider. For all transistors in the chain H?s = Vds and hence the saturation condition [VosI > [Hj sI “ 1H/’| is satisfied. The same current I^ias flows through the transistors and given to be

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V b l l

V T b l O

Figure 2.6: Voltage Divider Bias Chain

= M H . - H, - l l hl ) ^

/inCo.v, VF

{ - Y )i2{VoD - H l2 - |Vr,2|

(2..34)

(2.35)

But all the equations above valid only if the current drawn or supplied by the node to which bias voltage will be applied is much smaller than the bias current Jbias, i.e, /,· < /¡,,<,, is assumed. In our design, we will use this bias voltages to drive the gate of MOS transistors and hence we may use all those equations safely.Notice that only transistors Mi and M\2 have no body effect but for the others threshold voltages are different for different devices.

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-595.73mE -1 0.0: -2 0.0; -30.0: -40.0; -50.0; -60.0; -70.0: -8 0 .o: -90.O t ^ 0. 50.0m 100.0m Time (s) 150.Ora 180.0m

Figure 2.7: Available Bias Voltages

Threshold voltages are given by

Vti 1Vt2| = VT„ = \VtA + 7 ( \ / 2 | ^ , | + VoD - - v ^ ) (2.36) (2.37) I V V i i l = l l ^ T p l + 'ri\j2\4>A -l· Vdd - - y ^ ) (2.38) |Vt i2| = IVtpI (2.39) where Vrn and Vj'p are the threshold voltages of NMOS and PMOS transistors for VsB = 0 respectively. 7 is a device constant given by

^2,€<1 Nimp

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where e is the permittivity of silicon and Nimp is the density of impurity ions in the bulk.

The available bias voltages in the actual voltage divider chain of current source shown in Figure 2.7. From top of the plot, bias voltages correspond to Hid · · ·, Hi respectively.

Hio

= —3.99H and

Hi

= —90.99H has been used to

generate bias currents of current source and operational amplifier. If we used a PMOS transistor instead of Mi in bias chain, it would become impossible to generate the bias voltage of —90.99H since the threshold voltage of PMOS

Ml

would reach to about lOH and limits the value of

Hi

minimum

—

85H. NMOS transistor at Mi completely overcome that problem.

Calculated values of (W (L) ratios for the transistors in voltage divider bias chain of Figure 2.6 are shown in Table 2.2

Transistor (W/L) Ml 200 /1 /20 /i M2 15 /Í /20 n M3 200 fi /20 fi M4 200 fi /20 n Ms 200 /1 /20 n Me 200 n /20 fi Mr 200 fi /20 fi Ms 200 fi /20 fi. Ms 200 ft /20 /1 Mio 200 fi /20 fi Mil 200 fi / 2 0 fi M12 201 fi /20 fi

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C h a p ter 3

T est o f C urrent Source

3.1 Output Current Stability

The output impedance of current source simply modeled as in Figure 3.1 is very important since it determines the output current stability.

Figure 3.1: A simple model of current source

Output impedance of the current source is calculated by connecting an AC voltage source in place of K· Then R o is calculated using

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ib)

Figure 3.2; (a) Plot of Output Impedance (dB) vs. Frequency (Hz-log) and (b) Plot of Output Current (A) vs. Vo (V)

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(3 .1)

Frequency response of output impedance is plotted in Figure 3.2-a. It shows that at the expected operation range of a few kHz, the output impedance of current source is around giga ohms which is sufficient for required output sta bility. In fact, plot in Figure 3.2-b confirms our expectations. Output voltage

Vo is swept from —90F to +5V and change in current sunk is observed. Since

output voltage is changed dc-wise, current stability is controlled by output impedance of around 1 — 2GQ, which, in turn, will result in a deflection of

10.0350nA-9.9820nA= 53pA. AV; = 95F and A/„ = 53pA lead us to sensi tivity of

AIo

AVo = 0.56pA/V (3.2)

In other words, IF change in output voltage will cause a deflection of 0.56pA in output current which is negligible compared to the current level of lOnA. But we must be careful in trusting this performance. This plot is a result of DC analysis and therfore output impedance assumed is at its peak. In a normal operation , depending upon the frequency component of output voltage performance of current source will degrade.

3.2 Resistive Load

In order to show the effects of AC components at output voltage, configuration in Figure 3.3 is used. The variable load resistance as a function of time is first plotted in Figure 3.4. The rate of change in load resistance determine the AC component of output voltage. The faster Rl change , the lower is the output impedance encountered and the more deflection from lOnA is observed. Second plot in Figure 3.4 shows this phenomena. Third plot is the zoomed out repetition of the second plot, in which current stability can be observed more appropriately.

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Figure 3.3: Current Source Driving Variable Resistive Load

0. _{Time (s)} 1.50

Figure 3.4: (a): Rl vs. Time(s) (b): Output Current vs. Tim e(s), (c): Output Current vs. Time (s)-zoomed out

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3.3 Resistive and Capacitive Loads

Figure 3.5: Current Source Driving Variable Resistive Load and a Parallel Capacitcince

In actual use of this current source , the load will be not only a resistance but also a capacitance of order 1 — 2pF parallel to resistance as shown in Figure 3.5 . This capacitance causes problem in operation. The current source must have the ability of supplying lOnA current through the resistive branch. It is evident from the Figure 3.5 that the change in load resistance will cause an alternating voltage accross the load capacitance and the capacitance will withdraw or supply current proportional to the derivative of that voltage. The current through the capacitive branch is given to be

(3.3) and

Ir = h + I c (3.4)

Noting that the capacitive branch can supply or withdraw a current of many nano ampers, the current through the resistive branch may divert drastically from lOnA.

Figure 3.6 shows the simulation results of circuit in Figure 3.5. First plot of Figure 3.6 is the current through the resistive brajich which is equal to the

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200.0m 400.0m 6 0 0 .Ora 800.0m 1 .0 1.20 1.40

0. 1.50

Time (s)

Figure 3.6: (a): Current through resistive branch vs. Time (s) (b): Current through capacitive branch vs. Time (s) (c): Total current of source vs. Time (s)

sum of the capacitive current in second plot and total current supplied in third plot. It is obvious that if load resistance change more rapidly, larger capactive currents will be generated and more deflection from lOnA will occur.

Our next job in Chapter 4 is to add a capacitive current compensating branch to our original current source so that the current through the resistive branch is equal to lOnA no m atter what the load voltage variation is.

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C h a p ter 4

C a p a citiv e C urrent

C o m p en sa tio n

In order to compensate the current through the capacitive branch, we must first create a copy of that current. The only way of generating the capacitive current is to follow the mathematical relation that it obeys. We know that capacitive current is given by

th at is, we need a dilTeientiator to get the derivative of output voltage. (4.1)

4.1 Differentiator

Figure 4.1 is a simple differentiator. A straight-forward analysis show that dK-n

K =

-RdCd-d t ■ (4.2)

The block elements R j and Cj are used to obtain a certain multiple of input voltage derivative.

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VinO

o

Vo

Figure 4.1: Differentiator

V o

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Their values cannot be used arbitrarily in the case of a realistic opamp and one must be careful on the characteristics of the amplifier. If differentiator is connected directly to the output of the current source as in Figure 4.2 the differentiator capacitor C¿ will become parallel to load capacitance Cl

since it is connected in between output node of current source and virtual ground. In other words, the current we try to compensate increases. Since

0. _{Time (s)} 1 .5 0

Figure 4.3: Capacitive currents when differentiator connected, (a): Load I'esistance vs. Time (s), (b): Load capacitive current vs. Time (s), (c); Capacitive current due to differentiator vs. Time (s)

the differentiator capacitance is 50 times the load capacitance, it supplies or withdraws 50 times more current. In fact, the capacitive currents in (b) and (c) of Figure 4.3 are the same in shape but (c) is almost 50 times (b).

To overcome this problem, a buffer will be embedded between current source and differentiator, which is discussed in the next section. Opamp used is a realistic one and discussed in detail in Chapter 5. In simulation, the element values are chosen to be Rd = 100k, Cd = lOOp and Cl = 2pF.

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4.2 Buffer

An output stage must be able to deliver a considerable amount of power into a low-impedance load with acceptably low levels of signal distortion. Therefore, in general, it is required to have one or more of the following desirable properties [15]:

• Low output impedance • Large output voltage swing • Large output current swing • Almost unity gain

• Large input impedance

Vin

o-Vbias Vdd A M l _ 0 Vo M2 V Vss NMOS Buffer a Vbias Vdd

A

r

M2 _ 0 Vo M l Vin / PMOS Buffer

V

Vss

Figure 4.4: NMOS and PMOS Output Buffers

Figure 4.4 shows NMOS and PMOS output stages which can provide the above requirements.

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4.2.1 D C V oltage S hift

A close look to the circuit of buffers reveals that they also function as a DC Level Shifter. The (fT/L) ratios of transistors Mi and currents supplied by transistors M2 determine the gate-to-source voltage of transistors Mi which eventually leads to DC shift between output and input nodes. It is evident from the above two circuit that for NMOS Buffer

K> = Vi n _{- Kpal} (4.3) and for PMOS Buffer

K, = Kn + 1. (4.4) Then NMOS buifer fulfills a downward DC-shift while PMOS Buffer operate as an upward DC-level shifter. Available voltage in negative side is —95V and gives wider operation range, therefore it is better to use downward DC-level shifter , i.e NMOS buffer in order not to deal with degradation of the input signal. In Figure 4.5 the downward DC voltage shift characteristics of NMOS

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buffer is clearly observed. In both plots, upper wavefoms are the inputs and lower DC-wise shifted waveforms are outputs. The amount of shift is around IIV . Actually, the lower amounts of shift cannot be obtained using available supply voltages. That is because, Vsb of transistor Mi is much greater then zero and cause a large body effect. If there were no body effect

Kn - = Vto + {Vbias - Vss - Vto)

\

{W/L),

{WlL)r

and one can fully control DC voltage shift. But the large body effect cause (4.5)

Kn — Vout — Vt + (Vfctoi ~ Ks — Vto) jW /L ),

(W /L), (4.6)

where

Vt = Vto+ + Kut — \J‘^4>f)· (4.7)

We cannot reduce the DC shift below the threshold voltage which gets larger

Figure 4.6; NMOS Buffer DC-Level Shift vs Vin (V)

including the body-effect. The linearity of DC shift is examined in Figure 4.6. It is evident that &s input signal gets larger and larger, amount of DC shift also rise. The large signal behaviour of the buffer will cause the amount of DC shift to change.

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4.2.2 Sm all-Signal G ain

By small-signal analysis on NMOS buffer, it can be confirmed that

= ^ ______________ .

1 + (1^771611 + 5<il + g d 2 ) l 9 m \

(4.8)

Since Qmi |S'm6i |) 5(ii and Qd2 , voltage gain of buffer is approximated by

fS! 1. (4.9)

(a) of the Figure 4.7 shows that the voltage gain is very close to unity, (b) is the corresponding phase shift. In fact, gain of the buffer is not so much important in our circuit, because the gain lost at buffer stage can be compensated by changing the gains of subsequent stages.

4 .2 .3

O u tp u t Im p ed an ce

Using small-signal equivalent circuit of NMOS Buffer, expression of output impedance is calculated to be

f^out - 1

|< 7 m 6 l I + 5 'i i l + 9 d 2 + <7m l

(4.10)

There is a trade-off between the current through the buffer and output impedance. Higher levels of buffer current accompanies with the lower output impedance but this time we must be careful on power limitation. Fortunately, buffer in our circuit will drive a differentiator which has a high input impedance hence output impedance will not create a problem.

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Figure 4.7: (a): Small Signal Voltage Gain and (b): Phase Shift

4.3 Buffer and Differentiator

Remember that our aim in design of a buffer was to eliminate the effect of dif ferentiator capacitance C¿ on the current of resisistive load. After the insertion of NMOS buffer, circuit in Figure 4.2 turns into the circuit in Figure 4.8.

Referring to the Figure 4.8, differentiator capacitance C¿ and the current source output are completely isolated by means of buffer stage. But one must be careful in choosing the buffer stage because total gate capacitance of tran sistor Ml will cause a problem similar to that of Cj. Therfore, in design of buffer , the size of transistor Mi is kept as small as possible to keep its gate capacitance much lower than Cl. A proper design revealed that this gate ca

pacitance could be reduced to 0.23pF. This value is smaller than Cl but still its contribution to current through resistive load is important and must taken

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into account in setting compensation parameters.

V o

Figure 4.8: Differentiator and Buffer connected to the current source

Compared to Figure 4.3, the improvement of circuit performance after adding buffer stage is evident from Figure 4.9. First plot of that figure is the change in load impedance. It is redrawn here to get a feeling of relation between capacitive currents and load impedance change. In fact, assuming total current supplied by the current source fixed, derivative of the output voltage is proportional to the derivative of load impedance. The shape of capacitive current in (b) hence coincides with the waveform in (a) and is more recLSonable than that in Figure 4.3.

Third plot of the Figure 4.9 is the differentiator output. Using pre-defined parameters and an ideal opamp, the output voltage of differentiator must be equal to

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Figure 4.9: (a): Load Impedance vs. Time (s), (b): Current Through Load Capacitance, (c): Differentiator Output , (d): Current Through Load Resis tance

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But simulation using the realistic op-amp which will be discussed next gives

Vo = —4.55 X 10®/c- In setting of compensating branch parameters this value

should be taken into account.

Finally, (d) is the current of resistive load, which is equal to the sum of fixed current of lOnA and capacitive load current.

As a final remark, note that, DC shift of the current source output voltage after use of buffer cause no problem since it is directly input to a differentiator and completely eliminated.

4.4 Voltage Controlled Current Source

The next job is to convert that voltage into a current linearly and apply to the output node of original current source. There exist many types of VCCS’s but not many of them satisfy our desires. The required specifications of VCCS are as follows:

• Voltage to current conversion must be linear

• Governing equation must be independent of input voltage

• Depending upon the polarity of input signal, it must have the ability of supplying and withdrawing current

Circuit in Figure 4.10 satisfies all the requirements. Using Kirchoff’s Volt age and Current Laws, equations below can be written.

Kn — ( 4 .1 2 )

I2R2 + I4R4 — 0» ( 4 .1 3 )

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Figure 4.10: Voltage Controlled Current Source and Additionally, if then and /1 = / 2. R2 , R i ~ R z ~ R.2 — klii R\ = kRz·

Substituting Equations 4.17 and 4.18 into Equation 4.13

I2R1 d" JaRz — 0·

Using Equations 4.14, 4.15 and 4.19

I\R\

+

IzRz "VloRz —9

(4.15) (4.16) (4.17) (4.18) (4.19) (4.20)

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and hence

K'n + I0R3 — 0.

Then we conclude that the governing equation of the VCCS is Kn

/0 =

-(4.21)

(4.22)

The VCCS discussed carries all the nice properties desired but the only inherent disadvantage is that it requires exact matching of resistors. Other wise the relation in Equation 4.22 will no longer be valid. Circuit in Figure 4.10 is also capable of supplying or withdrawing current independent of load impedance. But note that, the value of load resistance determines the volt age at non-inverting pin of the operational amplifier. In addition to that, this voltage is transferred to the output pin of opamp depending upon the ratio of resistors,/; and hence there is always a danger of opamp being saturated. To overcome that, the resistor values and the voltage at non-inverting pin must be specified carefully.

4.4.1 In pu t Im p ed a n ce

The input impedance of VCCS is an important parameter because it loads the differentiator. A simple analysis assuming output and input impedances of opamp to be zero and infinity respectively reveals that

Rin = R3R1

R3

+

Rl

(4.23)

- By using Equation 4.23 we conclude that input impedance of VCCS may be very low depending upon the value of load impedance and hence load the dif ferentiator. The proper operation of differentiator is very important, hence an additional gain controlling stage with high input impedance will be embedded between differentiator and VCCS.

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4.5 Voltage Gain Stage

Circuit in Figure 4.11 is a Non-inverting Amplifier with high input impedance. It can be shown that

Ay — 1 -f

R i (4.24)

By choosing the values of resistors appropriately, any gain can be specified. R2

Figure 4.11: Non-inverting Amplifier with High Input Impedance

The input impedance is found to be

Rin - ARi

1 -f- R2 / R\ (4.25) where A is the open-loop gain and /?,· is the input impedance of the OpAmp. Since both have very high values , resultant input impedance is even larger than lii.

4.6 Current Compensating Circuit

Circuit shown in Figure 4.12 is the final topology including all the circuit elements described. Note that fixed lOnA current source has been modified to help the operation of VCCS. In fact, additional current mirror stages in

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the lOnA fixed current source provide a DC voltage of a few mV at node A to which feedback path from VCCS is connected. Element parameters are so chosen that current through the 2pF load capacitance is completely eliminated.

The overall circuit is designed for 2pF load capacitance but it can be ad justed for other values. For example, by changing only the parameters of non-inverting amplifier exact current compensation can be achieved.

For a proper operation of the circuit, the current generated by compeneistion branch must exactly match the load capacitive current when it arrives output node. It is observed that higher values of compensation current may cause a positive feedback and hence instability may occur. Therefore, in adustment of feedback parameters one must start from a compensating current less than actual load capacitive current and slowly increase the current gain. To be specific , lets define some current gain parameters;

G 1 Current Gain from node A to output. It is set to 1/545 G 2 Voltage Gain of Buffer. It is set to 0.937

G 3 Gain of Differentiator

G 4 Gain of Non-inverting Amplifier G 5 Current Gain of VCCS

Then, to avoid positive feedback and achieve exact compensation the necessary and sufficient condition is

G1G2G3GÎ1G5 — 1. (4.26) Since Gi and G2 are fixed

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G3G4G5 — 582 (4.27)

In fact, from circuit in Figure 4.12 it is found that G3 = 4550ifc , G4 = 2.3 and

Gs = i/l8 k . These values of gains confirms Equation 4.27.

Figure 4.13; Current through resistive load after current compensation

Plot in Figure 4.13 is the result of overall circuit. This result must be compared to (a) of Figure 3.6 in which current through resistive load without compensation is shown.

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For convinience, the currents through the load resistance are drawn for both cases: With current compensation and without current compensation. Plot in Figure 4.14 gives the chance of comparing these currents. Circuit performance is quite satisfactory.

Figure 4.15: Resistive load currents with and without compensation-Effect of feedback gain

If current compensation job is not successfully achieved it is better to change the value of resistors of non-inverting amplifier slightly. To show the effect of feedback gain let’s reduce it by reducing the gain of non-inverting amplifier. The feedback resistor in the amplifier is changed from 130A: to 30k which means

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be satisfied and not a full capacitive current compensation can be achieved. Referring to Figure 4.15, the current generated by feedback path does not m atch the capacitive current exactly and hence, even if current through resis tive load shrinks toward lOnA it does not have the desired shape. In order to provide a fixed lOnA current through resistive load , one must play with feedback gain.

In Figure 4.15 , the waveform with larger swing stands for the resistive load current without compensation and the other is that after compensation.

4 .6 .1

Feedback M o d el

At that step, we are ready to introduce the linear model of load capacitive current compensated current source. Main blocks of the current source are buffer, differentiator, non-inverting amplifier and voltage controlled current source. As a result of small signal analysis, it is found that all of these blocks have poles at many mega hertz. Corresponding gains of these blocks have been presented in Section 4.6. Referring to all of those information and circuit topology given in Figure 4.12 we derive the linear model shown in Figure 4.16.

For convinience some of the information given earlier will be repeated here.

G\ is the attenuation of current mirror stages from feedback connection point

.4 in circuit of Figure 4.12 to load and is equal to 1/545. R and C are load impedance and capacitance respectively. They are both assumed to be constant throughout the analysis.

G2 and p2 are the gain and pole of NMOS buffer. They are equal to 0.937 and 68MHz respectively. G3 = 4.55 x 10® and pa = 15MHz are the gain and pole of differentiator stage. For non-inverting amplifier stage G4 = 2.3 and p4 = 22MHz. Finally, VCCS has the pole of ps = 2MHz and gain of Gs = 1/18000.Gain stage K does not really exist but it serves for controlling the feedback gain during the stability analysis. Root-locus analysis is implemented by MATLAB using K as the gain parameter. Loop gain at which system become unstable is determined.

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Current Mirror

Attenuator

Load

Non-inverting Differentiator

Buffer

Amplifier

Figure 4.16: Feedback Control Model of Compensated Current Source

Figure 4.17 shows the locations of poles of overall system as K being the parameter. It is observed that the poles of final system are very close to those stated above. Dominant pole which is very close to origin, is generated by RC of the load and gets a minimum value of 50Hz when load impedance is lOM and load capacitance 2pF. Possible range of load impedance is from 4G to 8G and hence the dominant pole can move from 62.5Hz to 125Hz.

The gain K at which the real parts of the poles become positive is measured to be 7.827. Therefore, further increase in feedback gain makes the circuit unstable.

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Figure 4.17: Root-Locus Analysis

In order to decide how much this result fits the original circuit, open loop gain of original current source circuit is determined by means of HSPICE sim ulations for different feedback gains. Phase margins will provide the necessary information for stability.

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Figure 4.18; Open-loop gain of current source, (a) Gain (dB) vs. Freq (b) Phase vs. Freq - Feedback Gain(K)=1.3

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Figure 4.19: Open-loop gain of current source, (a) Gain (dB) vs. Freq (b) Phase vs. Freq - Feedback Gain(K)=3.47

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Figure 4.20: Open-loop gain of current source, (a) Gain (clB) vs. Freq (b) Phase vs. Freq - Feedback Gain(K)=5.20

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Figure 4.21: Open-loop gain of current source, (a) Gain (dB) vs. Freq (b) Phase vs. Freq - Feedback Gain(K)=5.86

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Figure 4.18 4.19 4.20 4.21 Open-Loop Gain (K) 1.30 3.47 5.20 5.86 Phase Margin 125° 30° UNSTABLE Table 4.1: Open Loop Gains and Phase Margins.

Open-loop gains and corresponding phase margins are shown in Table 4.1. Circuit become unstable whenever open-loop gain reaches the value of 5.86 for fixed value of load impedance. In fact, this result is very similar to that obtained from root-locus analysis. Comparing the gains 5.86 and 7.827, the first one is more reliable since it is obtained from the original circuit.

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C h a p ter 5

O p era tio n a l A m plifier

5.1 Introduction

An operational amplifier is one of the most versatile and widely used building blocks in linear circuit applications. Basically, operational amplifiers are direct coupled differential amplifiers with extermely high voltage gain, extremely high input impedance and very low output impedance. They are usually used with external feedback to achieve precision, gain and bandwidth control.

CMOS opamps contains NMOS and PMOS transistors all of which are operated in their saturation region. A practical opamp has a finite gain of order 60 — 120dB at low frequencies. There is always a DC offset voltage at the output and it is in the order of /rV at the input. The common mode signal amplification may not be equal to zero. This property is described by the parameter CMRR and it is a measure of opamp ability to suppress noise. The open-loop gain decreases with increasing frequency due to stray capacitances. The frequency at which open-loop gain reaches 1 is called unity-gain frequency and denoted by cuo. Then, if the phase at lOo is greater than —180®, the system

will be stable. Phase margin is defined as the phase at u>o plus 180®. Phase margin is a measure of opamp stability and must be set larger than 30®.

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5.2 Circuit Topology

Circuit in Figure 5.1 is the operational amplifier used in previous chapters. The input transistors M\ and M2 have symmetrical structures. A/3 and M4 are active loads and have also identical structures. They are also the governing transistors of current mirrors composed of M3-M5 and M^-Mq.

Mg , Mio and M i5 operate as a current source and supply the current that makes operational amplifier work. M7 and Mb are also current mirrors and provide a symmetrical operation. M3 and M u creates a current mirror structure and biases the output gain stage. M\Q-Mn and Mis-Mig pairs set two different source followers. They function as an output stage and a DC level shifter. These level shifters are used to obtain a zero offset at operational amplifier output.

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5.3 Test of Operational Amplifier

In order use an op amp properly, it must satisfy certain specifications. The values of open-loop gain, CMRR, output impedance, phase margin, available DC range and offset voltage are important parameters and must be set appro priately.

5 .3 .1 O p en -L oop G ain

To find the open-loop gain of operational amplifier which is given by

(5.1) configuration in Figure 5.2 is used. Plot in Figure 5.3 shows open-loop gain

£, Vout

in dI3 vs. frequency. From that plot it is measured that opamp open-loop 3 dB bandwidth is

B W = 3 M H z (5.2)

Low bandwidth is due to a pole close to jw axis and that pole is generated by very high impedance nodes in the circuit. Impedances mostly determined by

gd which is given by

\ Id

9d =

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The cliannel-length modulation parameter A is set to be 1/x by founders and therefore gd is at the level of picos. Inverse of gd gives impedance which become a considerably high value.

Advantage of low channel-length modulation factor is that very high gains can be easily obtained. It is therefore open-loop gain is in the orders of 1.30dB while 3-dB bandwidth is a few hertz. But the thing which is important is

G BW ^ gain-bandwidth product. It is given by G B W = A ,{a)B W

and hence it is equal to almost 11.5MHz.

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5.3.2 P h a se M argin

(a) and (b) in Figure 5.4 shows open-loop gain and phase respectively. It is measured that the phase at unity gain is around —150° and hence corresponds to a phase margin of 30°.

Figure 5.4: Determination of Phase Margin ; (a): Open-loop gain (dB) vs. Freq.(MHz), (b): Phase vs. Freq. (MHz)

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5 .3 .3

Offset V oltage

To find the offset voltage, configuration in Figure 5.5 has been used. The

Voltage

Figure 5.5: Determination of Offset Voltage

offset voltage at output is found to be —457.81/iV. This corresponds to input offset voltage of 144.7pV.

5 .3 .4

O utput Im p ed an ce

1 0 . 0

Frequency (Hz) ·

Figure 5.6: Output Impedance vs. Frequency[10Hz-10MHz]

Analog integrated circuit of a low level high voltage current source with capacitive load compensation

CAPACmVE

LOAD

COMPENSATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL AND

ELECTRONICS ENGINEERING

AND THE INSTITUTE OF ENGINEERING AND SCIENCES

OF BILKENT UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

MASTER OF SCIENCE

Mustafa Ertugrul ÖNER

Octqber,i&97

ANALOG INTEGRATED CIRCUIT OF A LOW

LEVEL HIGH VOLTAGE CURRENT SOURCE WITH

CAPACITIVE LOAD COMPENSATION

By

Mustafa Ertugrul Oner

October 1997

ABSTRACT

ANALOG INTEGRATED CIRCUIT OF A LOW LEVEL

HIGH VOLTAGE CURRENT SOURCE WITH CAPACITIVE

LOAD COMPENSATION

Mustafa Ertiigrul Öner

M.S. in Electrical and Electronics Engineering

Supervisor: Prof. Dr. Abdullah Atalar

October 1997

ÖZET

EDEBİLEN

DÜŞÜK SEVİYE YÜKSEK GERİLİM AKIM KAYNAĞI

TASARIMI

Mustafa Ertıığrul Öner

Elektrik ve Elektronik Mühendisliği Bölümü Yüksek Lisans

Tez Yöneticisi: Prof. Dr. Abdullah Atalar

Ekim 1997

ACKNOWLEDGEiMENT

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

C h ap ter 1

In tro d u ctio n

C h a p ter 2

C urrent Su p p ly B u ild in g B locks

2.1

Current Mirror

2.1.1

In trod u ction

A

A

A .

2,1.2

C urrent A m p lific a tio n /A tte n u a tio n

(

.

)

2.1.3

S atu ration C ondition

I<u

h =

K,

Ku

\Vasz\ = J ~

‘% />,.. +14-

K.

2.2

lOnA Current Source

A

I C

- n h r - l L

" • n i —

- I

□ H - i c :

P l - H r

2.2.1

O u tp u t Current S tab ility

1 + ^Vps

Id-

Av;

Ah =

2.3 Voltage Divider Bias Circuit

_{I C}