Temperature-dependent C-V characteristics of Au/ZnO/n-Si
device obtained by atomic layer deposition technique
A. Kocyigit1 · I. Orak2,3 · Ş. Aydoğan4 · Z. Çaldıran4 · A. Turut5
Received: 4 October 2016 / Accepted: 19 December 2016 © Springer Science+Business Media New York 2017
free charges in the interface. The series resistance (Rs) of
the device was taken into account to understand its effect on main electrical parameters, and it could be seen from these results that the Rs strongly depends on the device
tem-perature. The impedance (Z) values decreased with chang-ing from −1 to +2 V bias voltages and increaschang-ing tempera-ture. The barrier height which was obtained from the C−2-V
plots increased a slope of 0.00108 eV/K with a decrease in temperature from 160 to 340 K. It can be concluded that the Au/ZnO/n-Si device may be used and improved for next technological applications such as capacitor and memristor.
1 Introduction
There is a great interest in metal–semiconductor devices in the electronic industry owing to their versatile techno-logical applications [1–5]. Sometimes, metal oxide (ZnO, SnO2,…) and insulator layers insert between the metal
and semiconductor in order to control properties of these devices [6]. These properties contain diode parameters such as barrier height, ideality factor and interface states. There are many using areas of these devices such as rectifi-ers [7], inverters [8], polarity protection [9] and freewheel-ing diodes [10].
The ZnO has a high direct band gap of 3.37 eV, large exciton binding energy (60 meV) and very promising prop-erties, such as the combination of low costs, non-toxicity and low temperature deposition [11, 12]. The semiconduc-tor ZnO has also many using areas in electronic industry such as chemical sensors [13], varistors [14], solar cells [15], UV photo detectors [16], lasers [17] and light-emit-ting diodes [18]. It could be numbered many techniques to obtain the ZnO layers between the metal and semiconduc-tor such as spray pyrolysis [19], spin coating [20], atomic
Abstract Since the importance of Schottkky devices, Au/
ZnO/n-Si device were obtained, and the capacitance–volt-age (C-V) and conductance-voltcapacitance–volt-age (G-V) characteristics of Au/ZnO/n-Si device were studied using admittance spectroscopy at changing temperature from 160 to 340 K with 20 K intervals and −1 to +2 V bias voltage range. The interface thin film ZnO layer was deposited on the n-type Si wafer by atomic layer deposition technique (ALD) in order to obtain homogenous interface layer. The layer thick-ness of ZnO was taken as 10 nm by the resulting ZnO film growth rate at about 1.45 Å per cycle. This thin film layer was characterized with XRD and AFM analyses. It can be seen from the C-V curves of the device that the capacitance values increased in depletion region with increasing tem-perature and exhibited peaks towards to forward biases after 240 K temperature. The changing of capacitance values confirmed re-ordering and re-structuring of charges in the interface of the device with changing temperature. The G-V curves of the device also increased with increasing temper-ature and towards to forward bias voltages due to increasing
* A. Kocyigit
adem.kocyigit@igdir.edu.tr
1 Department of Electrical Electronics Engineering, Engineering Faculty, Igdir University, 76000 Igdir, Turkey 2 Vocational School of Health Services, Bingöl University,
12000 Bingöl, Turkey
3 Department of Physics, Faculty of Sciences and Arts, Bingöl University, 12000 Bingöl, Turkey
4 Department of Physics, Faculty of Sciences, Ataturk University, 25100 Erzurum, Turkey
5 Engineering Physics Department, Faculty of Engineering and Natural Sciences, Istanbul Medeniyet University, 34700 Istanbul, Turkey
layer deposition (ALD) [21]. Among these technique, the ALD has significant advantages because it has large area uniformity, definite thickness control, highly protective deposition, and ALD technique can be used under low tem-perature growth which is very important for the fabrication of low cost and flexible electronics [22].
To better understand the properties of metal–semicon-ductor devices, it should be obtained temperature depend-ent electrical characteristic of these devices. On the other hand, temperature dependent electrical characterizations provide more information about conduction mechanism, interface states and barrier inhomogeneity of metal–semi-conductor devices [23–26]. If the literature is investigated, it could be seen many studies about temperature depend-ent electrical characterization of differdepend-ent metal–semicon-ductor structures because of its importance. For example, Kumar et al. [27] investigated TiO2/Si MOS device at dif-ferent annealing temperature, and they found that electrical parameters were influenced changing temperature. Weich-sel et al. [28] studied temperature dependent capacitance effects on palladium zinc oxide Schottky structure, and they obtained changing capacitance and diode parameters with changing temperature. Reddy et al. [29] researched the temperature-dependent current–voltage (I-V) and capaci-tance–voltage (C-V) characteristics of Pt/Ti/n-InP Schottky structures. There are no so many investigations about the temperature-dependent C-V characteristics of Au/ZnO/n-Si devices in the literature.
In addition to above properties of Schottky devices, if a metal dopes on semiconductor surface, the obtained metal semiconductor devices exhibit a capacitor like behavior depending on frequency [30]. In this context, the aims of this study are to investigate the capacitor properties of the Au/ZnO/n-Si device at different temperatures from 160 to 340 K as step 20 K using impedance spectroscopy for tech-nological applications and to fill the literature about tem-perature dependent electrical properties of Au/ZnO/n-Si device.
2 Materials and methods
n-type Si wafer, which had (100) orientation and 7.3 × 1015 cm−3 carrier concentration with respect to
manufacturer specifications, was used for the fabrica-tion of the ZnO/n-Si heterojuncfabrica-tion. The n-type Si wafer was cut into pieces of 1.0 cm length and 1.0 cm breadth. Before using this wafer, it was polished and cleaned with various solvents, and then it was degreased consecutively in acetone and methanol for 3 min. After cleaning, the wafer was etched with H2SO4:H2O2:H2O (5:1:1) for 1 min
to remove the surface damages and undesirable impuri-ties. Gold was evaporated (thermal) on the back side of
the wafer for ohmic contact, and the n-Si/Au structure was annealed at 450 °C for 3 min in N2 atmosphere. The
thickness of metal coverage was determined using a quartz thickness monitor placed in close proximity to the Si sample. The ZnO layer was deposited on n-Si wafer with ALD technique as 10 nm thickness with 1.45 Å growth rate at per cycle. Au metal was evaporated on the ZnO surface as metallic contacts using mask which had 1.0 mm diameter holes on it. The device was character-ized with C-V measurements in the range of 160–340 K temperatures with 20 K intervals at 500 kHz frequency by using a homemade liquid nitrogen cryostat equipped with a temperature controller in darkness. The ZnO film layer in the device was also characterized with Bruker D8 Discover XRD and PSIA XE-100E model AFM.
3 Result and discussion
XRD patterns of the ZnO film have been shown in Fig. 1. According to this figure, only ZnO peaks can be seen from XRD pattern; (100), (103) and (201) peaks. The XRD pattern of the ZnO has indicated that the ZnO thin film was deposited successfully using by ALD technique on n-Si wafer surface.
2D and 3D AFM images of the ZnO thin film have been indicated in Fig. 2 for 40 μm x 40 μm wide area scanning. It can be seen from the AFM images that the ZnO surface has good homogeneity and smoothness. It can be said from this figures that ALD technique is very effective for smooth ZnO thin film layer.
Figure 3 has shown the C-V characteristics of Au/ ZnO/n-Si device at changing temperatures from160 K to
340 K and bias voltage from −1 to +2 V at 500 kHz fre-quency. It can be seen from this figure that the tempera-ture and applied bias voltage strongly have affected the capacitance behavior of the Au/ZnO/n-Si device. In the inversion region of the C-V characteristics, capacitance values almost have not influenced from temperature, but they have increased suddenly in depletion region due to narrowing depletion region with increasing forward bias and increasing temperature. The capacitance graphs have exhibited peaks above 240 K temperatures, and the peak positions have changed towards to negative biases. These peaks and changing at their positions could be ascribed to reordering of the near midgap interface states and series resistance with changing temperature [31–35].
In addition, the increasing capacitances and intensity of peaks can be attributed to changing freeze-out effect in charges with increasing temperature [36–38]. The high capacitance values near room temperature imply that the device may be used at room temperature for capacitor and memristor applications [39, 40].
The G-V plots of the Au/ZnO/n-Si device at various tem-peratures for 500 kHz frequency have been shown in Fig. 4. It can be said from this figure that the conductance values have been influenced also from applied forward biases and increasing temperatures [40]. Increasing forward bias from zero to 0.5 V value, the conductance values have increased suddenly. These increasing can be attributed to narrowing depletion region and charges which have enough energy to escape from traps in the interface [32]. The changing tem-perature from 160 K to 340 K, the conductance values have increased depending on increasing mobility of charge car-ries and decreasing secar-ries resistance of the device [41].
It should be also investigated the series resistance (Rs)
of the device to more understand the device properties. The series resistance can cause a serious error in the extraction of interfacial properties and doping profiles from admit-tance measurements, and it can limit the sensitivity of the small-signal steady-state methods. Therefore, it is not pos-sible series resistance to be neglected. The series resistance
Fig. 2 AFM images of the ZnO
layer surface onto n-Si substrate
Fig. 3 (online color) C-V characteristics of Au/ZnO/n-Si device at
various temperature and 500 kHz Fig. 4 (online color) G-V characteristics of Au/ZnO/n-Si device with
equation is given by following formula depending conduct-ance and capacitconduct-ance values:
where Gmand Cm are measured conductance and
capaci-tance, respectively, and 𝜔 is angular frequency and equal to 2𝜋f. Rs values were calculated from Eq. (1) using the
meas-ured conductance and capacitance values for each tempera-ture in Figs. 1 and 2. Then, the series resistance–voltage
(R–V) curves of the Au/ZnO/n-Si device in the temperature
range of 160–340 K have been indicated in Fig. 5.
As can be seen from Fig. 5, the Rs values have
remained almost unchanged in the reverse bias region (negative voltages) and at high voltages in the forward bias region (positive voltages) for each temperature. Fur-thermore, it can be seen that the observed series resist-ance peaks in the forward bias region have shifted from about 0.60 V at 160 K to 0.25 V at 300 K. The peak posi-tion of the series resistance has increased very slightly towards to negative voltage with increasing temperature. When the interface state density in equilibrium with the semiconductor becomes lower than expected one, the series resistance effect is more obvious. Therefore, it can be said that the interface state density is lower in this voltage range. The interface states in this voltage range are called the near midgap states. These kinds of results can be seen in the literature. For example, D.A. Jameel et al. [42] fabricated PANI/(100) GaAs and PANI/ (311)B GaAs devices by a simple technique to fabricate hybrid devices, where polyaniline thin films was called PANI. They [42] observed two peaks for the temperature-dependent series resistance–voltage curves of the PANI/
Rs= Gm G2 m+ ( 𝜔Cm)2
(100) GaAs. One of the peaks appeared in the reverse bias region and the other in the forward bias region, and one peak in only forward bias region for the PANI/(311)B GaAs device for each temperature. The series resistance value for both devices increased with decreasing temper-ature in the reverse and forward bias regions. Yakupha-noglu [43] obtained the series resistance–voltage curves from C-V and G-V characteristics of the Al/p-Si/n-CdO diode under various frequencies at 300 K. He observed two peaks 0.0–1.0 V range in forward bias region of the
series resistance–voltage curves. This behavior had been
attributed to the changes and distribution density of inter-face states [35, 44].
Figure 6 shows impedance-voltage (Z-V) curves of Au/ ZnO/n-Si device in changing temperature from 160 K to 340 K at 500 kHz frequency. According to this figure, the impedance values generally have decreased with increas-ing temperature in a given voltage. This decreasincreas-ing can be attributed to freezing effect which is eliminated with increasing temperature, and charges need less energy to run away from traps at high temperatures [37, 45]. On the other hand, this case may be ascribed to the contributions of majority carriers and interface states to the conductiv-ity [29, 41]. In addition, the Z values have decreased with changing bias voltage from −1 V to about 0.5 V (deple-tion region), and then they have remained constant in the accumulation region. Also, these changing in the Z val-ues with temperature and voltage prove particular distri-bution of interface states or presence of interfacial layer ZnO effect [40, 41].
The C− 2-V plots of the Au/ZnO/n-Si device
depend-ing on temperature have been shown in Fig. 7. It can be seen from this figure that these plots are linear and almost
Fig. 5 (online color) Series resistance–Voltage (R-V) curvess of Au/
parallel each other which indicates uniform dopant con-centration and ideal rectifying contact of the device [36,
45, 46]. Also, it can be said from these plots that charges cannot follow ac signal in the depletion region [45]. Fur-thermore, V0 intercept potentials (Table 1), which was
obtained from the C−2-V plots, have decreased almost
periodically with increasing temperature. These changing can be ascribed to interface states of the device [47].
By using C−2-V graphs, Fermi energy level (E
F), barrier
height (Φb), maximum electric field (Em), concentration
donor atoms (Nd) and effective density of conduction band
(Nc) were calculated, and the values of these parameters
were tabulated in Table 1. EF values have increased with
increasing temperature due to increasing charge carriers in the interface of device or increasing donor concentrations [32, 45, 47]. Em values have decreased with increasing
tem-perature owing to the increasing charge carriers.
It could be seen from Fig. 8 that the barrier heights and donor concentrations of device have changed depending
on temperature. The barrier heights have decreased a slope of 0.00108 eV/K with an increase in temperature from 160 to 340 K. This decrasing can be ascribed that increasing temperature has caused the decrease the band gap of Au/ZnO/n-Si device [32, 40, 45]. However, donor concentration plot has some fluctuations, but it gener-ally has not so changed with increaing temperature (in Table 1). This case may be compared with some results in the literature [25, 45].
Phase angle (θ) versus voltage graphs of the device have been shown in Fig. 9 for changing temperatures from 160 to 340 K. Phase angel values have not changed from −1 V to about 0.25 V, but they have decreased with increasing temperature after 0.25 V. It can be said from this results that device is more capacitive in the forward biases rather than reverse biases because phase angel val-ues have remained constant at 90° at reverse biases [48].
Fig. 7 (online color) C−2-V plots of Au/ZnO/n-Si device changing temperature from 160 K to 340 K
Table 1 The some electrical
parameters of Au/ZnO/n-Si device obtained C− 2-V graphs
T(K) Nd (1015 cm− 3) Nc (1017 cm− 3) EF (eV) eV0 (eV) Φb (eV) Em (104 V/m)
160 6.16 1.70 0.046 0.90 0.94 3.96 180 6.86 2.02 0.053 0.97 1.02 3.72 200 6.83 2.37 0.061 0.93 0.10 3.46 220 6.69 2.73 0.070 0.87 0.94 3.16 240 6.51 3.12 0.080 0.88 0.96 2.86 260 6.34 3.51 0.090 0.75 0.84 2.50 280 6.43 3.93 0.099 0.73 0.83 2.26 300 6.79 4.35 0.108 0.76 0.86 1.93 320 6.58 4.80 0.119 0.72 0.84 1.69 340 6.34 5.25 0.130 0.67 0.80 1.45 125 175 225 275 325 375 Temperature (K) 1015 1016 Carrier Concentration (c m -3) 0.50 0.75 1.00 1.25 1.50 Barrier Height, b (C -V ) (eV) Au/ZnO/n-Si Carrier Concentration Barrier Height Fit to experimental data
b(C Φ
Φ
-V) = -0.00108T + 1.17 eV
Fig. 8 (online color) Barrier height and donor concentration
4 Conclusion
The ZnO layer in the Au/ZnO/n-Si device was obtained by using ALD technique and it has 10 nm thicknesses after then device completed as a Schottky device. XRD studies of ZnO film have shown that film has only ZnO peaks, and AFM images indicated homogenous and smooth film sur-face. The C-V and G-V measurements for the Au/ZnO/n-Si device were performed by changing temperature from 160 to 340 K with 20 K intervals. The C-V plots of Au/ ZnO/n-Si device have increased with increasing tempera-ture in the depletion region, and they have exhibited peaks in about 0.5 V forward biases after 240 K. The tempera-ture-dependent G-V plots of the device have also increased with increasing temperature in a given bias voltage because of increasing free charges in the interface. The impedance values have decreased towards to forward bias voltage and increasing temperature. Some electrical parameters such as Fermi energy level (EF), barrier height (Φb) and maximum
electric field (Em) were calculated from C−2-V pots and
dis-cussed in details. Phase angle values have not changed in negative biases but they have decreased forward bias with increasing temperature. The Au/ZnO/n-Si device may be used and improved for future technological applications.
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