Monitoring the operation of a graphene transistor in an integrated
circuit by XPS
Pinar Aydogan
a, Osman Balci
b, Coskun Kocabas
b, Se
fik Suzer
a,* aDepartment of Chemistry, Bilkent University, 06800, Ankara, TurkeybDepartment of Physics, Bilkent University, 06800, Ankara, Turkey
a r t i c l e i n f o
Article history: Received 22 March 2016 Received in revised form 20 June 2016
Accepted 20 June 2016 Available online 2 July 2016 Keywords: Graphene XPS Contact resistance Integrated circuit Transistor
a b s t r a c t
One of the transistors in an integrated circuit fabricated with graphene as the current controlling element, is investigated during its operation, using a chemical tool, XPS. Shifts in the binding energy of C1s are used to map out electrical potential variations, and compute sheet resistance of the graphene layer, as well as the contact resistances between the metal electrodes. Measured shifts depend on lateral positions probed, as well as on polarity and magnitude of the gate-voltage. This non-contact and chemically specific characterization can be pivotal in diagnoses.
© 2016 Elsevier B.V. All rights reserved.
1. Introduction
After the discovery of the two-dimensional honeycomb struc-tured carbon about a decade ago, colossal academic activity has been witnessed around a single or few-layers of graphene. [1,2]
Even a greater activity has also been devoted to the technological developments in terms of incorporation of graphene to the existing and well-developed infra-structure.[3e6]For characterization of the materials involving graphene, and more importantly, the de-vices fabricated from them, in addition to electrical, chemical characterization is also needed. In that respect, most of the commonly utilized optical techniques can only give indirect infor-mation about the electrical properties seeked. [7e14] Similarly, information derived using the conventional and powerful electron spectroscopic techniques, like Auger (AES), Ultra-Violet (UPS), and X-ray (XPS) photoelectron spectroscopies are also indirect, when it comes to electrical properties.[15e19]However, under appropriate conditions, all of the electron spectroscopic techniques are capable of reflecting local electrical potentials developed, intentionally or not, on the analyzed material or the device, since such potentials are embedded into the measured kinetic energy of the ejected
electrons. Accordingly, difference between the obtained binding energy and the tabulated one gives the chemically-addressed local electrical potential, which has been extensively utilized by our group and others to harvest electrical information, difficult to obtain by other methods.[20e23]Using this methodology, we have previously reported on analyses of a device using graphene as the resistive sheet between the two electrodes,[20] and in another device where the graphene layer was operated in the back-gated transistor geometry.[21] The present work extends it to analyze one of the transistors of the 64 elements of an IC-device, where C1s binding energy position is measured with lateral resolution to probe and map-out electrical properties of the transistor. Investi-gation of a single element out of the 64, is presented as“a proof of principle”, since extension to the others are straightforward. 2. Experimental details
A picture of the device together with a survey XP spectrum of a graphene-only region is given inFig. 1(a), where the dominating O1s feature belongs to the SiO2 substrate, since probe depth is
about 10 nm, but the C1s peak has the peak position of graphene at 284.7 eV. We synthesize single layer graphene on an ultra-smooth copper foil (purchased from Mitsui mining and smelting company, LTD, B1-SBS) by using a chemical vapor deposition (CVD) system connected to a vacuum pump. We heat up copper foils to 1035C
* Corresponding author.
E-mail address:suzer@fen.bilkent.edu.tr(S. Suzer).
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Organic Electronics
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under 100 sccm H2flow. We, then, grow graphene by flowing 10
sccm CH4to the chamber for 1 min at that temperature. The partial
pressures of the H2and CH4are 1.5 Torr and 3 Torr, respectively,
during the growth process. We cool down the chamber at a rate of 10C/s to room temperature, while 100 sccm H2flows. To transfer
graphene on SiO2substrates, wefirst coat the copper foil with the
Shipley 1806 resist and dry them by annealing overnight at 80C. Then, we etch the graphene grown copper in FeCl3aqueous
solu-tion. After washing and drying the resist-graphene stack, we put it on SiO2substrate and heat the resist-graphene-SiO2stack at 70C
for 2 min and at 120C for 20 s. This process ensures that the resist-graphene stack perfectly sticks to the SiO2surface. We dissolve the
dry resist with acetone andfinally obtain a graphene transferred on SiO2substrate. To fabricate back-gated graphene transistors on Siþ/
SiO2substrate, we evaporate 50 nm Au for source and drain
con-tacts to the graphene. After isolating each transistor channel with a reactive ion etching (RIE) process, we evaporate 5 nm-Ti and
100 nm-Au to extend the area of source and drain contacts. Mechanically strong metal contacts are required for wire-bonding. The fabricated transistors used in this work have 0.5 mm channel width and 1.0 mm channel length. Schematic drawing of the fabricated transistors is shown in Fig. 2(a). To measure the electrical performance of the fabricated transistors, we use HP-4153 probe station.
3. Results and discussion
We apply1 V bias between the source and drain electrodes and measure the current as a function of the gate voltage, shown in
Fig. 2(b). The result of the electrical-only measurements indicates the Dirac point to be near 0 V, and other Current-Voltage charac-teristics are depicted inFig. 2(c). The calculatedfield effect mobility of the device used in this study is around 820 and 600 cm2/V for holes and electrons, respectively (see the Supplementary
Fig. 1. (a) A survey XP spectrum recorded from the graphene-only part of one of the transistors. Areal intensity maps of the entire IC recorded in the snap-shot mode with 200mm X-ray spot size and 200mm steps of; (b) Au4f, and (c) C1s. (d) Picture of the IC inserted into the load-lock of the instrument.
Fig. 2. Electrical characterization of graphene transistors. (a) Schematic drawing of a back-gated graphene transistor is shown. (b) Transfer curve of one of the graphene transistors as a function of back gate voltage. Red line shows the drain current with an applied bias of1 V and blue line shows the corresponding resistance of graphene as a function of the gate voltage. (c) Output curves of one of the transistor as a function of bias with varying gate voltages.(For interpretation of the references to colour in thisfigure legend, the reader is referred to the web version of this article.)
Information (SI) section and Fig. S1), where the mobility is calcu-lated using the maximum transconductance of the device. Once the integrity of the transistors has been established by electrical mea-surements, further contacts are attached for XPS characterization, a picture of which was given inFig. 1. The entire IC is inserted into the analysis chamber of the Thermo Fisher K-Alpha X-ray photoelec-tron spectrometer, which uses monochromatic AlK
a
(hy
¼ 1486.6 eV) as the excitation source. Some of the measure-ments are done only in the source-drain, while the other in the source-drain-gate geometry. Therefore, the instrument is modified to provide two external voltage biases, where one is used as the source and the other as the gate, while the drain is grounded. Using the intensity of the O1s peak of the substrate and the C1s of gra-phene from the survey spectrum of the gragra-phene-only region shown inFig. 1, it is possible to estimate the thickness of the gra-phene layer as ~1.1 nm. Computational details are given in theSI section.InFig. 1, areal intensity (computed area) maps of the entire IC recorded in the snap-shot mode with 200
m
m X-ray spot size and 200m
m steps are also shown for the Au4f and C1s peaks. Since the probe depth of XPS is about 10 nm, gold electrodes and also the gold wire connections are easily identified, while carbon is every-where. It is also possible to record the data with smaller spot size (50m
m) of and steps (50m
m), and zooming to only one of the transistors, as shown inFig. 3, where the intensity of the C1s and Au4f are shown as areal maps (a) and (c). In the same Figure the peak positions are shown as regular scanned spectra recorded in the line-scan mode with inherently better precision in (d) and (f), while aþ3 V bias is applied to the source electrode, and both the drain and the gate are grounded.The extracted binding energies are shown inFig. 3(e) for both peaks as a function of lateral position, and the actual spectra are reproduced in theSI section as Fig. S3. The binding energy of the Au4f7/2peak, which is commonly used as a reference, is 84.00 eV,
and it is exactly what is measured at the grounded electrode. However, it is measured as 86.94 eV at the source, yielding a dif-ference of 2.94 eV which reflects faithfully the applied voltage bias ofþ3 V, within the precision of our measurements. The measured difference in the position of the C1s peak across the electrodes is less precise and is 2.6 eV, i.e. 0.3 eV less. This small but significant difference can be attributed to the contact resistance(s) between the graphene and the gold electrodes, since application of 3 V causes a sizable current of ~2.6 mA, passing between the metal electrodes, consistent with the geometry of the graphene layer. The contact resistance, especially in devices with smaller dimensions is known to adversely affect the performance. [24e30] Therefore, location, as well as information related with its chemical nature is highly desirable. Besides the conventional electrical-only mea-surements, Kelvin probe force microscopy is the only other tool which can locate and quantify contact resistance(s),[27]but again it, too, falls short when it comes to chemical specificity. Hence use of XPS for this purpose is very unique.
In order to harvest the effect of gating, instead of applying a voltage bias, a current bias needs to be imposed, since the gate is the current controlling element of the circuit, which requires two biases. That is what is implemented for the data shown inFig. 4, where a constant voltage bias ofþ3 V is applied to the source through a precision 1 k
U
series resistor, and a second variable voltage bias is applied to the gate, while grounding the drain, as schematically shown in the samefigure. Here again, the voltage drop across the gold electrodes, as well as the potential variations through the graphene sheet, under three different gate voltages, are measured through the positions of the Au4f7/2 and C1s peaks,respectively, which are given inTable 1. Using these data together with a simple equivalent circuit model, both the sheet as well as the contact resistances can be obtained for all 4 different operational conditions of the transistor, in an all non-invasive fashion (details are given in theSI section). The values obtained are consistent with
Fig. 3. XPS data of one of the transistors recorded with 50mm X-ray spot size and 50mm steps of; (a) Areal intensity maps of C1s, and (c) Au4f peaks. A schematic representation of zooming to a single transistor connected in the source-drain configuration while the gate is grounded is displayed in (c). Spectra recorded in the line-scan mode are shown in (d) and (f), while the binding energy positions of the C1s and Au4f7/2are displayed in (e).
P. Aydogan et al. / Organic Electronics 37 (2016) 178e182 180
our previous electrical-only measurements,[29]and also with re-ported ones. It must also be stressed that extracted values of the transistor using XPS, as given inTable 1, differs from those depicted inFig. 2using electrical means. Such a difference is common since, the XPS measurements are performed in vacuum, in the absence of air and humidity, whereas the electrical measurements are carried out in air ambient, and the position of the Dirac point can deviate significantly between the two diverse conditions.
4. Conclusions
In summary, through application of electrical bias, XPS is shown to be able to extract electrical parameters of an isolated graphene-based transistor of a 64-element IC during its operation in a chemically specific and non-contact fashion.
Acknowledgments
This work is supported by the 2Dfun Project in the FLAG-ERA Joint Translational Call, 2015 within the Graphene Flagship and also by TUBITAK, the Scientific and Technological Research Council of Turkey, through the Grant No. 215Z534.
Appendix A. Supplementary data
Supplementary data related to this article can be found athttp:// dx.doi.org/10.1016/j.orgel.2016.06.027
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