Turkish Journal of Computer and Mathematics Education Vol.12 No.10 (2021),
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FinFET based high Performance BZFAD Multiplier for IOT Applications
Alluri Navaneetha1, Kalagadda Bikshalu2
1Mahatma Gandhi Institute of Technology, Hyderabad-500075, India. 2KU College of Engineering and Technology, Warangal-506009, India. 1neethaalluri@gmail.com, 2kalagaddaashu@gmail.com.
Article History: Received: 10 January 2021; Revised: 12 February 2021; Accepted: 27 March 2021; Published
online: 28 April 2021
Abstract :- In this paper FinFET based low power BZFAD multiplier for IOT applications is proposed. At present society is need
of low power IOT devices such as Bluetooth, Wi-Fi, RFID and Zig-Bee to connect the things to real world. FinFET BSIM CMG model files for the feature size 7 nm, 10 nm, 16 nm and 20 nm are used to analyze FinFET based BZFAD(Bypass zero feed adder directly) multiplier using licensed SymicaDE software tool. Static and dynamic power dissipation is investigated for FinFET based BZFAD multiplier. As the technology node decreases simulation results proved that power dissipation of multiplier circuit reduces and its value is less compared to MOSFET based multiplier circuits, FinFET based Array multiplier, Vedic multiplier circuits. The proposed FinFET multiplier can be used for low power IOT devices such as wireless sensor networks, and RFIDs which operates with low power batteries with more battery life.
Keywords: Low Power (LP),Internet of things(IOT),FinFET,Metal oxide semiconductor Field effect transistor
(MOSFET),Complementary metal oxide semiconductor (CMOS ),BZFAD(Bypass zero feed A directly) 1. Introduction
At present development of every section of society takes place with the usage of IOT technology.IOT technology is used in wide area of applications such as Embedded Systems, mobile computing, energy system, grid, health, transportation and environment requires devices and circuits which operate atlow power (LP) design. Future technologies such as cloud computing, Fog computing, big data, distributed computing utilizing IOT technology need circuits which work on high secure, high speed, low area, low power. The high-performance circuits can be designed by using advanced devices such as FinFET compared to MOSFET. For low leakage power and miniaturization in transistors control of channel by the gates is better in FinFET device. Portability is an important aspect for IOT devices along with low battery power and high security. Portability is achieved by scaling of device. At reduced technology below 20 nm FinFET has less energy compared to other technology nodes which presented by Dinesh Kumar in research article [1].At the technology node below 20 nm FinFET emerged as leading technology as it overcomes short channel effect compared to MOSFET [2].Senthil Kumar in research article shown that and gates, Vedic multiplier designed by FinFET has low power compared to MOSFET [3].
In digital circuits such as CPU, multipliers are important component in which speed and power requirement is main concern. To reduce the power dissipation in multiplier switching activity has to reduced [4]. Many Researchers have done work to reduce the power dissipation for different multipliers [[5]-[7]]. Rajshree Shanmugam shown in research article on comparative analysis of various multipliers in that array Multiplier has more power and Baugh Woolley multiplier has low power and high speed [8] which was implemented in Xilinx ISE 8.1 making use of VHDL programming Language. Large area is occupied by tree multipliers when used in high performance circuits. carry select adder used in radix multiplier requires more transistors which consumes more power. Less area and simple in design are obtained by using multipliers based on radix and shift architecture [9]. Already authors have done research on conventional multiplier and BZFAD multiplier using 130 nm MOSFET CMOS technology [4]. The result showed BZFAD has less power compared to conventional . Analysis of FinFET BZFAD multiplier from 20 nm to 7 nm is not done till now in the existing literature which can be used for the design of FIR Filter in which DSP processor is used for IOT applications such as wireless sensor networks, RFID etc.
The main objective is towards low power multiplier circuits compared to the existing FinFET Array Multiplier [2], FinFET Vedic multiplier
[3] and MOSFET conventional multiplier & BZFAD [4].Heat dissipation is proportional to power. More heat dissipation results due to more power which decreases speed and reliability. So, the requirement for IOT devices such as smart environment, smart health and smart transportation invokes to make the devices for low power.
M.Mottaghi-Basterji [4] presented a paper based on low power architecture BZFAD (By pass zero feed A directly) based on add and shift architecture, using 130nm CMOS technology has low power compared to the conventional multiplier. V.M. Senthil Kumar [3] presented a article,in this article it is shown that MAC unit, RAM or ROM, Adder, multiplier units in the discrete wavelet transform the existing CMOS discrete wavelet transform has more power than FinFET discrete wavelet transform which is implemented using 32 nm BSIM Files. Anubhuthi Mittal [10] presented article in this article simulation results shown that add & shift Wallace tree (WT) and Vedic
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multiplier used for the multiplication. Anubhuthi Mittal[10] results shown that reduced area and delay are obtained by using add & shift multiplier implemented on FPGA Spartan 3 using Xilinx ISE 8.1.1.1 Organization of paper
Section2 presents the background of FinFET device. Section 3 and 5 presents the methodology and power dissipation results of FinFET based BZFAD low power multiplier. Section5 presents results and discussion comparison of proposed FinFET multiplier with existing multiplier. The proposed FinFET multiplier shown low power and area compared to the existing one. Analysis of FinFET multipliers from 20 nm to 7 nm shown the result that at the reduce length of channel dynamic power dissipation and static power dissipation decreases. Section 6 concludes the paper.
2. Background
FinFET is a 3D device in which plain of wafer perpendicular to silicon body [1]. The gate of the FinFET is wrapped on channel. FinFET can have one, two, three and four gates wrapped on channel. Channel is controlled by gates which reduce short channel effects [12]. Compared to MOSFET, FinFET has better gate control which results faster switching speed, higher on current, lower leakage. FinFET can be operated in 2 modes a) Independent gate mode (LP) b) shorted gate mode (SG).In the Independent Gate Mode four terminals are present in FinFET. Independent gate mode also called LP mode used to reduce threshold voltage. In this mode back and front gate is connected with separate inputs.
In the Shorted Gate (SG) 3 terminals are present in FinFET. Front gate and back gate both are connected together with same input. At technology node below 20 nm MOSFET suffer from short channel effects such as more leakage power, threshold variations [13]. FinFET device is designed to reduce short channel effects. FinFET is fabricated on thin silicon insulator [3]. To minimize the power and reduce threshold voltage gate work function of the FinFET device is used. FinFET is emerged as promising device in literature to provide solution to the problem takingplace due to reduced technology node[14].FinFET fabrication is compatible with MOSFET for rapid deployment [15]-[16].
Figure 1. FinFET device
FinFET based low power Multiplier BZFAD
In conventional multiplier if LSR [0] value is “0” the accumulator is added with MSR register and zeros then 1-bit right shifting operation is performed. If the multiplier LSR [0] value is “1” then accumulator is added with MSR register and A input then 1-bit right shift operation is performed. Each bit of multiplieris tested and the result is placed in Partial Product Register (MSR, LSR). For completion of N-bit multiplication it requires 2*N clock cycles due to unwanted transition when LSR [0] is “0” to overcome we are using BZFAD.
In BZFAD when the B input bits are “0” the addition operation is bypassed and the Bypass register data is feed in to Feeder and P- Latch register. When the B input bits are “1” the addition operation is executed between Feeder and A input and the result is stored in Feeder and P-Latch. This leads to reduce the clock cycles, for completion of N-bit multiplication it requires only N clock cycles.
4. Low Power Multiplier (BZ-FAD)
In the proposed low power multiplier (BZ-FAD) a ring counter is used which makes shift of “1” from right to left. B[n] is selected by ring counter in nth cycle. Low power ring counter is used to minimize the switching activity. P-latch is used to store the lower half of the partial product, which makes use of klatches for k-bit multiplier. The least significant bit PP[0] of the product is stored in Plow of right most latch. Latch is opened properly by ring
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counter. nth bit of final product is sampled by nth latch. In the next cycle next bits are finalized and stored inrespective latches. The lower and higher halves of partial product form the final product result, when the last bit is stored in the left most latch. In this method shifting of lower half of partial product is not done only higher part of partial product is shifted. Comparing with conventional multiplier, BZFAD has low power due to following reasons 1.higher valve of partial product is shifted.2.Lower halve is implemented with latches instead of flipflops.Compared to carry select,carry look ahead,carry skip,conditional sum adders ripple carry adder has least average transition per addition.Due to low transition per adder ripple carry adder is used in proposeddesign.Figure 2. Architecture of FinFET based BZFAD multiplier
Figure 3. Simulation results of FinFET based BZFAD multiplier for A=0011,B=0011 the product value is 00001001 which is given in the simulation result as P0—P7 at the clock cycle of 4 and reset value 0
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Figure 4. Flow chart and low power and high speed BZFAD multiplier
Table 1: Ring Counter Truth Table
Ring CounterOutput Res et Clock R[3] R[2] R[1] R[0] 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
Table 2: Analysis of Low Power Multiplier BZFAD Partial Product R ST C LK Ring Coun ter B[ n] Adde r [4:0] Bypas s Feed er (MSR) P- Latc h (LSR)
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1 0000 0 0000 0 0000 0000 0000 0 0001 1 0001 1 0001 0001 0001 0 0010 1 0010 0 0010 0010 0001 0 0100 0 0010 1 0001 0001 0001 0 1000 0 0010 0 0000 0000 1001 B[n] Selected Output 0 BypassRegister 1 AdderoutputTable 3 : Static Power (µW) Comparison
Technolog y 20 nm 16 nm 14 nm 10 nm 7 nm Supply Voltage (V) 0.9 0.85 0.8 0.75 0.7 BZFAD 207.5 2 154.8 7 235.6 5 50.97 2.75 2
Table 4 : Dynamic Power (µW) Comparison
Techn ology 20 nm 16 nm 14 nm 10 nm 7 nm Supply Voltage (V) 0.9 0.85 0.8 0.75 0.7 BZFA D 1087. 76 679.8 2 856.3 2 351.7 5 186.17
Table 5:Clock cycles and transistor count comparison
Parameter Transistor count
Clock Cycles / Multiplication
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Figure 5. Comparsion of dynamic power dissipation of FinFET based BZFAD multiplier at different technology nodes.
Figure 6 .Comparsion of static power dissipation of FinFET based BZFAD multiplier at reduced technology nodes.
5. Results and Discussion
Simulation results of FinFET based BZFAD multiplier using 7 nm BSIM Files [15] shown that the no of clock cycles for multiplication in BZFAD is 4 and transistor used is 1610.. The static power dissipation in FinFET based BZFAD is 2% less than that of Array multiplier. Dynamic power dissipation of BZFAD less than that of that of vedic multiplitier ,array multiplier, existing MOSFET based conventional and BZFAD multiplier.The results shown that static and dynamic power dissipation of BZFAD multiplier reduced as technology node reduces. Table 7 data results shown that comparison of static power dissipation of FinFET based BZFAD multiplier has low power dissipation compared to the existing MOSFET based BZFAD and conventional multiplier, FinFET based array and Vedic multiplier.
DYNAMIC POWER DISSIPATION
Technology(nm) Power dissipation(µW)
186.17
20 16 10
351.75 679.82
1087.76
STATIC POWER DISSIPATION
Length of the channel(nm) Power dissipation(µW)
50.97
20 16 10 7 2.75
154.87 207.52
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Table 6.Comparsion of static power dissipation of existing multipliers and proposed designed BZFAD multipl ier
Multiplier Width Technology Static Power
(µW)
Ref. Paper No.
Published Year
Conventional 16-bit 0.13 µm (MOS) 10.824 [4] 2008
BZFAD 16-bit 0.13 µm (MOS) 7.576 [4] 2008
VEDIC 4-bit 7 nm (FinFET) 175.68 [3] 2019
Designed BZFAD(Proposed)
4-bit 7 nm (FinFET) 2.75
Figure 7 .Comparison of static power dissipation of existing multiplier and proposed designed BZFAD Multiplier
Figure 8. Comparsion of no of transistors and no of clock cycles used in proposed BZFAD Multiplier
Static power(µW
)
200 100
Vedic Array Designed BZFAD
No of Transistors and clock cycles used in BZFAD Multiplier
2000 1000
Series1 No of transistors No of Clock cycles
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6. Conclusion
The Multipliers are extensively used in Digital Signal Processor (DSP). With advancement in VLSI technology as the DSP has become increasingly popular over the year, the high-speed realization of multiplier with less power consumption has become much more demanding. The operation of FIR filter is mainly depended on the multiplier design. Conventional (Add and Shift) multiplier and Bypass Zero Feed A direct (BZFAD) multiplier is implemented by using BSIMCMG files and SymicaDE tool at FinFET 7 nm, 10 nm, 14 nm, 16 nm and 20 nm technologies . Simulated multipliers shown that the BZFAD is fastest than conventional multiplier with respect to clock cycles. The power dissipation, transistor count of BZFAD is less than the conventional multiplier. By observing these comparisons, we can state that BZFAD multiplier improves the speed of operation, reduces the area in terms of transistor counts and reduces the Power dissipation.To improve the multiplier performance the BZFAD is Compared with conventional and other multipliers for implementation which can be used in future microprocessors and microcontrollers.
Acknowledgement
Apart of research work is contributed by K.MuraliMohan Undergraduate student of Mahatma Gandhi Institute of technology. The authors would also like to thank symica software company for providing licensed Symica DE software tool and college for providing support and encouragement.
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