The C-V characteristics of the Cu2WSe4/p-Si heterojunction depending on wide range temperature

https://doi.org/10.1007/s10854-019-01553-0

The C–V characteristics of the  Cu

WSe

/p‑Si heterojunction depending

on wide range temperature

Adem Koçyiğit1 _{· Hayreddin Küçükçelebi}2 _{· Adem Sarılmaz}3 _{· Faruk Ozel}3,4 _{· Murat Yıldırım}5

Received: 4 March 2019 / Accepted: 21 May 2019 / Published online: 25 May 2019 © Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract

Cu₂WSe₄ nanosheets were synthesized by hot-injection method and employed as interfacial layers between the p-Si and Au metal via spin coating technique. The capacitance–voltage (C–V) and conductance-voltage (G–V) measurements were performed on the Cu2WSe4/p-Si heterojunction device depending on wide range temperatures from 80 to 400 K by 40 K

steps. The device exhibited decreasing capacitance behavior with increasing temperature at the inversion region because of the interface states and series resistance. The conductance values increased with increasing temperature owing to increasing free charge carriers. The series resistance (Rs) and interface states density (Nss) were extracted from C–V and G–V

measure-ments and discussed in the details. The results highlighted that the electrical parameters are a strong function of the voltage and temperature. The Au/Cu₂WSe₄/p-Si device can be employed for controllable capacitor applications.

1 Introduction

Chalcogenides are semiconductor materials and have a good optical property which is an adjustable band gap energy between 1 eV and 3 eV depending on their compositions, good thermal and electrical properties [1, 2]. They can be synthesized in amorphous or crystalline form [3]. Those properties made them very interesting materials for various applications such as data storage, switching, and biomedi-cal applications [4]. Ternary transition metal chalcogenides which are symbolized as AB₂X₄ (A, B are transition metals,

X = S, Se, Te) have a great interest among the other chal-cogenides in the last decades because of their potential application in the solar energy, electrochemical hydrogen reactions and photocatalysis [5–8]. Ternary transition metal chalcogenides can be prepared by various techniques such as chemical vapor deposition or vapor transport, solvother-mal, hydrothermal or hot-injection method [9–13]. Of the ternary transition metal chalcogenides, Cu2WSe4 can absorb

the light in the visible range and can be use for electronic applications [13, 14].

The Cu₂WSe₄ can be employed as the interfacial layer between the metal and semiconductor and can provide the electrical properties of the metal–semiconductor devices for control [14, 15]. The capacitance behaviors of the Cu₂WSe₄ can be determined between the metal and semiconductor as the interfacial layer [16–18]. Especially temperature depend-ent C–V and G–V characteristics of the metal–semiconduc-tor devices give good information about the conduction mechanism, barrier inhomogeneity and the interface states of the metal semiconductor devices. According to our best knowledge, there is no studies about temperature depend-ent electrical characterization of the Cu₂WSe₄ between the metal and the semiconductor as the heterojunction device.

In here, we fabricated Cu2WSe4 nanosheets with the

hot-injection method and performed the nanosheets as the inter-facial layer between the Au metal and p-Si to obtain Au/ Cu₂WSe₄/p-Si heterojunction with spin coating technique. The heterojunction device was characterized by temperature

* Faruk Ozel

farukozell@gmail.com * Murat Yıldırım

muratyildirim@selcuk.edu.tr

1 _{Department of Electrical Electronic Engineering,} Engineering Faculty, Igdir University, 76000 Igdir, Turkey 2 _{Department of Physics, Faculty of Science, Selcuk}

University, 42130 Konya, Turkey

3 _{Department of Metallurgical Science and Materials} Engineering, Faculty of Engineering, Karamanoğlu Mehmetbey University, 70200 Karaman, Turkey 4 _{Karamanoglu Mehmetbey University, Scientific}

and Technological Research and Application Center, 70200 Karaman, Turkey

5 _{Department of Biotechnology, Faculty of Science, Selcuk} University, 42130 Konya, Turkey

dependent C–V measurements by 40 K steps from 80 to 400 K temperature range.

2 Materials and methods

Cu2WSe4 nanosheets were obtained by the hot-injection

method in argon medium. 163  mg WCl4 and 170  mg

CuCl2.2H2O were mixed in 12 ml oleylamine (OLA) in

three-neck flask. The obtained solution was heated up to 180 °C. The solution color changed from black to blue with increasing temperature. Then, 198 mg Se powder dissolved in OLA and temperature of the Se solution increased to 300 °C. The obtained Se solution was injected to the first solution and then stirred 30 min and cooled down to 120 °C. 2 ml oleic acid was included to combined solution. The solu-tion was centrifuged for 10 min in toluene and ethanol. Thus, the Cu₂WSe₄ nanosheets were obtained and dried at 70 °C.

To obtain Au/Cu2WSe4/p-Si device, the (100) preferred

orientation p-type Si wafer was cut into 2 cm2 _{small pieces}

and cleaned in acetone, deionized water and propanol in an ultrasonic bath. The cleaned Si wafer pieces were dried and dumped into HF:H2O (1:1) solution to remove the

oxide layer and impurities from the surfaces for 30 s. Then, to obtain ohmic contact on the back surface of the wafer pieces, a 100 nm Al layer was evaporated towards the sur-face. The pieces were annealed for 5 min in N2 atmosphere

at 500 °C. A spin coater was employed to obtain a Cu2WSe4

nanosheets film on the front surfaces of the Si wafer pieces at 2000 rpm and for 30 s. An Au layer was vaporized to the Cu2WSe4 nanosheets film towards the surfaces to

com-plete Au/Cu2WSe4/p-Si devices as the rectifying contact.

The schematic diagram of the obtained devices has been indicated in Fig. 1.

Detailed description of XRD and EDS [14], TEM, HR-TEM, SAED pattern of the Cu2WSe4 nanosheets film can be

found in our previous study [15]. The C–V and G–V meas-urements data were obtained by Keithley 4200 SCS for vari-ous temperatures in a cryostat.

3 Result and discussion

The C–V characteristics of the Au/Cu₂WSe₄/p-Si devices have been shown in Fig. 2 for various temperatures increas-ing from 80 to 400 K via 40 K steps at 500 kHz frequency. The capacitance values of the device decreased with increas-ing temperature at inversion region and indicated peaks towards depletion region. The peak behavior and shift at the peak positions can be attributed to reordering of the interface states and changes in series resistance [19–22]. However, the capacitance values remained constant at depletion and accumulation regions due to the changes of the temperature and voltage. While the capacitance values decreased with increasing temperature, the peak sharpness increased owing to interface states at the inversion region [23, 24]. Such behavior is hard to find in the literature because generally the capacitance values decrease with decreasing temperature depending on freeze-out effect of the carriers towards low temperatures [25, 26]. This behavior can be attributed to the interfacial layer Cu2WSe4 nanosheets. In addition, the

device has MOS type C–V curves for various temperatures at 500 kHz frequency [23, 27, 28].

The conductance voltage (G–V) plots of the Au/ Cu2WSe4/p-Si heterojunction have been indicated in Fig. 3 in

various temperatures. The G values increased with increas-ing temperature at the inversion region and stayed constant at the depletion and accumulation regions. The increase at the conductance values with increasing temperature can be attributed to increasing mobility of the charge carriers in the interface of the heterojunction device [29]. The increasing temperature also caused peaks for higher temperatures than room temperature. The peaks can be attributed to interface

Fig. 1 The schematic diagram of the Au/Cu2WSe4/p-Si devices

-4 -2 0 2 4 0.0 0.5 1.0 1.5 2.0 2.5 Capacitance (nF) Voltage (V) 80 K 120 K 160 K 200 K 240 K 280 K 320 K 360 K 400 K

Fig. 2 The C–V plots of the Au/Cu₂WSe₄/p-Si heterojunction for var-ious temperatures

states effect [30]. The peak position changed towards deple-tion region with increasing temperature.

The resistance (Ri) value of the heterojunctions is

inves-tigated to understand the device characteristics better. The resistance of the heterojunction can be calculated from below formula depending on measured capacitance ( Cm )

and conductance ( Cm):

where 𝜔(= 2𝜋f ) is angular frequency. The Ri versus voltage

plots of the Au/Cu2WSe4/p-Si heterojunction have been

indi-cated in Fig. 4 depending on the measurement temperature in the range of 80 and 400 K. According to Fig. 4, the Ri

values are sensitive to the temperature and voltage changes. In other words, the Ri values exhibited peaks at the

inver-sion region and the peak intensity and position increased with increasing temperature and shifted slightly towards the inversion region. The peak behavior of the Ri can be

attributed to that of the trapping charges which have enough energy to escape from the localized traps between the semi-conductor and metal [31–33]. In the accumulation region, the Ri values slightly increased with the increasing

tempera-ture but stayed almost constant via changing the voltage for each temperature.

Figure 5 displays the C−2_{-V graphs of the Au/Cu}

2WSe4/p-Si

heterojunction in various temperatures at 500 kHz frequency. The C−2_{-V plots exhibited almost linearity and parallel to each}

other in various temperatures, but there are some deviations from linearity which can be attributed to interfacial Cu2WSe4

nanosheets film layer and non-ideal metal semiconductor structures [34–36]. In addition the non-linear plots of the (1) R_i= Gm G2 m+ ( 𝜔C m )2

C−2_{-V can be attributed to that of interface states can follow}

ac signal at 500 kHz frequency easily [37].

The below formula gives the relation between the capaci-tance and the potential [38]:

where Vd , 𝜀0 , 𝜀s , A , and Na represent diffusion potential,

the permittivity of space, the permittivity of semiconduc-tor, metal contact area and concentration of acceptor atoms, respectively. The Vd is determined in the x-axis

extrapola-tion of the C−2_{-V plot and the slope of this plot with V}

d (2) C−2= 2(Vd+ V ) q𝜀₀𝜀_sA2N_a -4 -2 0 2 4 0 2 4 6 8 10 12 14 16 Conductance (mF/s ) Voltage (V) 80 K 120 K 160 K 200 K 240 K 280 K 320 K 360 K 400 K

Fig. 3 The G–V characteristics of the Au/Cu2WSe4/p-Si heterojunc-tion for various temperatures

-4 -2 0 2 4 0 100 200 300 400 500 Ri (Ω ) Voltage (V) 80 K 120 K 160 K 200 K 240 K 280 K 320 K 360 K 400 K -2.5 -2.0 -1.5 -1.0 100 200 300 400 500 Ri (Ω ) Voltage (V)

Fig. 4 The R–V plots of the Au/Cu2WSe4/p-Si heterojunction for var-ious temperatures -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0 0.8 1.6 2.4 3.2 4.0 1/ C 2(1/F 2)( x 10 19) Voltage (V) 80 K 120 K 160 K 200 K 240 K 280 K 320 K 360 K 400 K

Fig. 5 The C−2_{-V graphs of the Au/Cu}

2WSe4/p-Si heterojunction device for various temperatures

helps to determine other parameters such as barrier height (Φb), Fermi energy level (EF), maximum electric field (Em)

and width of the depletion region (Wd). These parameters

were calculated and listed in Table 1 in various tempera-tures. According to Table 1, while the Na , EF, Φb and Em

values increased with increasing temperatures, Wd values

decreased. The increasing at EF values can be attributed to

increasing donor concentrations and charge carriers with the increasing temperature [39]. While the increase at Φb values

can depended on directly increasing diffusion potential, the decrease at the Wd values can be attributed to the increasing

donor concentrations with increasing temperature.

Hill-Coleman technique enables us to determine the inter-face states density (Nss) of the metal–semiconductor

hetero-junctions via the next equation [40]:

(3) Nss= 2 qA (Gm∕𝜔)max ((Gm∕𝜔)maxC0x)2+(1 − Cm∕C0x )2

where C0x is the capacitance of the interfacial layer and

cal-culated with below equation:

In this equation, the Cma and Gma symbolize the

meas-ured capacitance and conductance at accumulation region, respectively. The calculated Nss and Rs values were tabulated

in Table 1 in various temperatures.

Figure 6a, b shows the temperature dependent profile of the Nss, Φb and Na , Rs. According to Fig. 6, while the Nss,

Φ_b and Na values increased with increasing temperature, the

Rs values increased up to 240 K and then slightly decreased

towards 400 K. This can be attributed to the semiconductor properties of the Cu₂WSe₄ nanosheets interfacial layer.

To remove the series resistance effects of the device, the interface states, the capacitance and conductance values (4) C_0x= Cma [ G2 ma ( 𝜔C_ma )2 ]

Table 1 _{The temperature dependent electrical parameters of the Au/Cu2WSe4/p-Si heterojunction device calculated form the C}−2_{-V graphs} f (kHz) Na (1016 cm−3) Vi (V) EF (meV) Φb (eV) Em (104 V/m) Wd (10−5 cm) Nss (eV−1 cm−2) Rs (Ω)

80 1.18 1.96 0.036 1.97 8.38 4.68 2.94 × 109 _55.5 120 1.19 1.99 0.053 2.02 8.46 4.70 6.17 × 109 _62.2 160 1.25 2.06 0.071 2.11 8.85 4.68 6.33 × 109 _69.7 200 1.27 2.09 0.088 2.16 9.00 4.67 8.04 × 109 _74.2 240 1.30 2.11 0.105 2.20 9.12 4.64 1.07 × 1010 _75.4 280 1.33 2.12 0.122 2.23 9.24 4.61 1.31 × 1010 _73.5 320 1.36 2.13 0.139 2.26 9.36 4.58 1.58 × 1010 _68.8 360 1.37 2.12 0.156 2.27 9.41 4.54 1.99 × 1010 _63.5 400 1.40 2.13 0.172 2.31 9.54 4.51 2.28 × 1010 _60.0 100 150 200 250 300 350 400 2.00 2.08 2.16 2.24 2.32 Temperature (K)

Barrier Height (eV)

(a)

(b)

should be corrected [41]. The adjusted capacitance and con-ductance values are calculated in below equations:

where 𝛼 is given by the following equation:

Figure 7 indicates Cadj versus voltage plots of the Au/

Cu2WSe4/p-Si heterojunction device in various

tempera-tures. The corrected capacitance values increased with increasing temperature and exhibited peaks at the inversion region. The peak property of the capacitance values can be attributed to interface states [42]. There are no changes at the capacitance values in the depletion and accumulation region with the temperature and voltage changes.

The Gadj versus voltage plots of the Au/Cu2WSe4/p-Si

heterojunction have been shown in Fig. 8 in various tem-peratures. The corrected conductance values increased with increasing temperature and exhibited peaks towards the higher temperature and inversion region. The peak behav-ior at the conductance values can be attributed to interface states effect via changing temperature [43]. The G_adj did not change at the depletion and accumulation region via the changing temperature and voltage.

(5) C_adj= [ G2_m+( 𝜔C_m)2 ( 𝜔C_m )2 + 𝛼2 ] C_m (6) G_adj= [ G2_m+( 𝜔C_m)2 ( 𝜔C_m )2 + 𝛼2 ] 𝛼 (7) 𝛼= G_m− [ G2_m+( 𝜔C_m)2 ] Rs

4 Conclusion

The Cu2WSe4 nanosheets were fabricated by hot-injection

method and deposited between the metal and p-Si by spin coating technique to obtain Au/Cu₂WSe₄/p-Si heterojunc-tion device. The obtained device was characterized by C–V and G–V measurements in various temperatures from 80 to 400 K by 40 K steps at 500 kHz frequency. The C–V and

G–V characteristic of the Au/Cu₂WSe₄/p-Si heterojunc-tion device exhibited peaks at the inversion region and did not change at the depletion and accumulation region. The peak behavior of the device in various temperatures was attributed to interface states and series resistance. The Au/ Cu2WSe4/p-Si heterojunction device has MOS type C–V

curves. The resistance values of the device are sensitive to temperature and voltage changes. The electrical param-eters such as EF, Φb, Em and Wd were calculated by the

C−2_{-V plots and discussed in details depending on the}

tem-perature changes. The corrected capacitance and conduct-ance values were calculated to see interface states effect on the device. The Cu₂WSe₄ nanosheets can be used in capacitor application as an interfacial layer in the industry.

Acknowledgements The authors would like to thank to Selçuk University BAP office (Project Number 17401159) and Karamano-glu Mehmetbey University (Grand Number: 32-M-16) for Scientific Research Foundation. -4 -2 0 2 4 0 10 20 30 40 50 60 Cadj (nF) Voltage (V) 80 K 120 K 160 K 200 K 240 K 280 K 320 K 360 K 400 K

Fig. 7 C_adj-V plots of the Au/Cu₂WSe₄/p-Si heterojunction device in various temperatures -4 -2 0 2 4 0 20 40 60 80 100 120 140 160 180 Gadj (mF/s) Voltage (V) 80 K 120 K 160 K 200 K 240 K 280 K 320 K 360 K 400 K -5 -4 -3 -2 -1 0.000 0.005 0.010 0.015 Gadj (mF/s) Voltage (V)

Fig. 8 G_adj-V plots of the Au/Cu2WSe4/p-Si heterojunction device in various temperatures

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