DESIGN, IMPLEMENTATION,
MANUFACTURING AND MEASUREMENTS
OF DICKSON CHARGE PUMP CIRCUITS
FOR CAPACITIVE MICROMACHINED
SENSOR BIASING
a thesis submitted to
the graduate school of engineering and science
of bilkent university
in partial fulfillment of the requirements for
the degree of
master of science
in
electrical and electronics engineering
By
Z¨
ulkarneyn S
¸i¸sman
January 2019
Charge Pump Circuits for Capacitive Micromachined Sensor Biasing By Z¨ulkarneyn S¸i¸sman
January 2019
We certify that we have read this thesis and that in our opinion it is fully adequate, in scope and in quality, as a thesis for the degree of Master of Science.
Abdullah ATALAR(Advisor)
Hayrettin K ¨OYMEN
Barı¸s BAYRAM
ABSTRACT
DESIGN, IMPLEMENTATION, MANUFACTURING
AND MEASUREMENTS OF DICKSON CHARGE
PUMP CIRCUITS FOR CAPACITIVE
MICROMACHINED SENSOR BIASING
Z¨ulkarneyn S¸i¸sman
M.S. in Electrical and Electronics Engineering Advisor: Abdullah ATALAR
January 2019
This work presents the design and testing process of Dickson charge pump cir-cuits for micromachined sensor biasing. Necessary blocks of different types of circuits with different functions are examined such as inverters, diode connected MOSFETs, ring oscillators, bond PADs, charge pump stages. Layouts for these circuits are designed and simulated using extracted parameters. The designed circuits are operating using a 5 Volts supply to generate output voltage levels
of 12-15 Volts. Finalized layouts are placed on a chip using 0.35µm process.
Designed chip is manufactured and bonded on a test PCB for verification. Mea-surement results are given and analyzed. Layout and circuit design improvements are proposed and simulated for proof. Steps for future improved designs and pre-cautions are provided. This work enables the way for better functioning charge pump topologies and designs in the future.
OZET
KAPAS˙IT˙IF M˙IKRO ˙IS
¸LEMEL˙I SENS ¨
OR S ¨
UR ¨
ULMES˙I
˙IC¸˙IN D˙ICKSON S¸ARJ POMPASI DEVRELER˙IN˙IN
TASARIM, GERC
¸ EKLEME, ¨
URET˙IM VE ¨
OLC
¸ ¨
UMLER˙I
Z¨ulkarneyn S¸i¸sman
Elektrik ve Elektronik M¨uhendisli˘gi, Y¨uksek Lisans Tez Danı¸smanı: Abdullah ATALAR
Ocak 2019
Bu ¸calı¸sma kapasitif mikroi¸slemeli sens¨orlerin s¨ur¨ulmesi i¸cin Dickson ¸sarj pompası devrelerinin tasarım ve test s¨ure¸clerini incelemektedir. Birbirinden farklı i¸slevlere sahip devrelerin alt bile¸senleri incelenmi¸stir, ¨orne˘gin: invert¨or devreleri, diyot ba˘glantılı tranzist¨orler, halka osilat¨orler, ba˘glantı pedleri, ¸sarj pompaları. Bu devrelerin layout tasarımları yapılmı¸s ve parazitik elemanlar hesaplanıp devreler sim¨ule edilmi¸stir. 5 Volt kaynak gerilimi ile beslenen devreler ile 12-15 Volt ¸cıkı¸s gerilimi elde edilmesi ama¸clanmı¸stır. Sonlandırılan layout tasarımları0.35µm’lik ¨
uretim teknolojisine sahip bir ¸cipe yerle¸stirilmi¸stir. Tasarlanan ¸cip ¨uretilmi¸s ve bir test kartına tel ba˘glaması ile ba˘glanmı¸stır. Ol¸c¨¨ um sonu¸cları sunulmu¸s ve incelenmi¸stir. Sonu¸clardan yola ¸cıkarak layout ve devre tasarımlarının daha iyi ¸calı¸sacak versiyonları tasarlanmı¸s ve sim¨ule edilmi¸stir. Gelecekteki tasarımların daha sa˘glıklı yapılabilmesi i¸cin gereken adımlar sunulmu¸s ve alınabilecek ¨onlemler ¨
onerilmi¸stir. Bu ¸calı¸sma gelecekte istenilen ¸sartları fonksiyonel olarak sa˘glayan ve do˘grulanabilecek olan tasarımların yaratılması i¸cin bir ¨on ayak olmu¸stur.
Acknowledgement
I am grateful to Prof. Abdullah ATALAR for his guidance, patience, technical, theoretical expertise and hindsight through which he helped me finish my master’s studies. I have acquired invaluable skills, knowledge and experience during my
studies thanks to him. I am also thankful to Prof. Hayrettin K ¨OYMEN and
Prof. Barı¸s BAYRAM for being in my thesis committee and helping me improve the quality of this thesis.
In addition, I want to acknowledge the TUBITAK-BIDEB for the national MSc. scholarship. I would also like to thank my fellow group members Murat G¨ungen and Cem B¨ulb¨ul for helping me during my studies.
I would like to thank Bilkent University Administration for being understand-ing, constructive and helpful whenever I faced bureaucratic issues. I want to
thank M¨ur¨uvet PARLAKAY for helping me since my undergraduate days for 8
years and always being supportive of students. I would also like to thank Metek-san Defense family and my coworkers for being supportive of my studies.
Finally I would like to thank my family for being there and supporting me unconditionally whenever things got hard.
Contents
1 Introduction 1
1.1 Motivation and Background . . . 1
1.2 Research Objectives . . . 5
1.3 Thesis Outline . . . 5
2 Overview of Charge Pump Topologies 7 3 Design and Simulation 16 3.1 Design Specifications . . . 16
3.2 Detailed Analysis of Dickson Charge Pump . . . 18
3.3 Sub-Circuit Blocks . . . 25
3.3.1 CMOS Inverter for Ring Oscillator . . . 25
CONTENTS vii
3.3.5 Off-PMOS Delay Block . . . 37
3.4 Main Circuit Blocks . . . 38
3.4.1 11 Stage Ring Oscillator . . . 38
3.4.2 Three Stage Charge Pump . . . 45
3.4.3 Four Stage Charge Pump . . . 48
3.5 Post-Layout Simulations and Layout Considerations . . . 60
3.5.1 Post-Layout Simulations . . . 60
3.5.2 Final Layout Design . . . 64
4 Experimental Results 72 4.1 Test PCB Design . . . 72
4.2 Measurements . . . 74
4.2.1 11 Stage Ring Oscillator Measurements . . . 74
4.2.2 Four Stage Charge Pump with Capacitive Delay Measure-ments . . . 78
4.2.3 Leakage Delay, Off PMOS Delay, Three Stage Pump, Four Stage Pump Measurements . . . 83
4.3 Layout Design Results and Notes for Future Studies . . . 85
List of Figures
1.1 Boost Converter Topology . . . 2
1.2 Bootstrap Circuit . . . 3
1.3 High Side Hot Swap Controller . . . 4
2.1 Greinacher Voltage Doubler . . . 8
2.2 Cockcroft & Walton Voltage Converter . . . 9
2.3 Dickson Charge Pump . . . 10
2.4 Bootstrapped Dickson Charge Pump . . . 11
2.5 Transfer switch in ON state. a) Dickson Charge Pump, b) Boot-strapped Dickson Charge Pump . . . 11
2.6 Boosted Charge Pump . . . 12
2.7 Double Charge Pump Topology . . . 13
LIST OF FIGURES ix
3.1 Desired Output Voltage Waveform . . . 17
3.2 Dickson Charge Pump with Stray Capacitances . . . 18
3.3 Dickson Charge Pump Clock Signals . . . 18
3.4 Dickson Charge Pump Node Numbering . . . 19
3.5 Dickson Charge Pump Node Pumping Phase . . . 20
3.6 Diode Connected NMOS Transistor . . . 24
3.7 1-Stage Inverter with Capacitive Load Circuit . . . 26
3.8 1-Stage Inverter Layout . . . 27
3.9 1-Stage Inverter with Capacitive Load Transfer Characteristics Post-Layout Simulation . . . 28
3.10 1-Stage Charge Pump Circuit . . . 30
3.11 1-Stage Charge Pump Layout . . . 31
3.12 1-Stage Charge Pump Diode Characteristics Post-Layout Simulation 32 3.13 Capacitive Delay Timer Circuit . . . 33
3.14 Capacitive Delay Timer Circuit Layout . . . 34
3.15 Capacitive Delay Timer Circuit Post-Layout Simulation . . . 35
3.16 Capacitance vs Delay . . . 35
3.17 Leakage Delay Timer Circuit . . . 36
3.19 OFF PMOS Delay Timer Circuit . . . 37
3.20 OFF PMOS Delay Timer Circuit Layout . . . 38
3.21 11 Stage Ring Oscillator Circuit . . . 39
3.22 Ring Oscillator Output Stage Circuit . . . 40
3.23 11 Stage Ring Oscillator Circuit with Output Stage . . . 41
3.24 11 Stage Ring Oscillator Transient Simulation with Output Stage 42 3.25 11 Stage Ring Oscillator Layout . . . 43
3.26 11 Stage Ring Oscillator with Output Stage Layout . . . 44
3.27 Ring Oscillator Post-Layout Simulation . . . 45
3.28 Three Stage Charge Pump Circuit . . . 46
3.29 Three Stage Charge Pump Layout . . . 47
3.30 Threee Stage Charge Pump Transient Spice Simulation . . . 48
3.31 Four Stage Charge Pump Circuit . . . 49
3.32 Four Stage Charge Pump Layout . . . 50
3.33 Four Stage Charge Pump Spice Simulation . . . 51
3.34 Output Voltage Reduction Control Circuit . . . 52
3.35 Four Stage Charge Pump Circuit with Capacitor Programmable Output Voltage Reduction . . . 53
LIST OF FIGURES xi
3.37 Four Stage Charge Pump Transient Simulation with 5nF External
Delay Capacitor . . . 55
3.38 Four Stage Charge Pump Circuit with Surface Leakage Delayed Output Voltage Reduction . . . 56
3.39 Four Stage Charge Pump Layout with Leakage Delayed Output Voltage Reduction . . . 57
3.40 Four Stage Charge Pump Circuit with OFF PMOS Delayed Out-put Voltage Reduction . . . 58
3.41 Four Stage Charge Pump Layout with OFF PMOS Delayed Out-put Voltage Reduction . . . 59
3.42 11 Stage Ring Oscillator Post-Layout Simulation with Output Stage 61 3.43 Three Stage Charge Pump Post-Layout Simulation . . . 62
3.44 Four Stage Charge Pump Post-Layout Simulation . . . 63
3.45 Four Stage Charge Pump Post-Layout Simulation with 5nF Exter-nal Delay Capacitor . . . 64
3.46 VDD PAD Schematic . . . 65
3.47 GND PAD Schematic . . . 66
3.48 Signal PAD Schematic . . . 67
3.49 Powercut Schematic . . . 68
3.50 Chip Layout . . . 69
4.1 Test PCB for Bonding . . . 73
4.2 Bonded Chip Microscope Photo . . . 74
4.3 Ring Oscillator Measurement Results . . . 75
4.4 Ring Oscillator Buffer Connection . . . 76
4.5 Ring Oscillator Updated Output Stage Layout . . . 77
4.6 Ring Oscillator Updated Output Stage Simulation Result . . . 78
4.7 Four Stage Charge Pump Circuit with Capacitor Programmable Output Voltage Reduction . . . 79
4.8 Four Stage Charge Pump with Capacitive Delay Post-Layout Sim-ulation . . . 81
4.9 Updated Four Stage Charge Pump with Capacitive Delay Post-Layout Simulation . . . 82
List of Tables
4.1 11 Stage Ring Oscillator Measurement Results . . . 76
4.2 Four Stage Charge Pump with Capacitive Delay Measurement
Re-sults . . . 80
Chapter 1
Introduction
1.1
Motivation and Background
The majority of electronic devices and circuits have a single connection to a single power source. That power source can be a battery, a line connected power supply or a combination of both. In either case, in most situations, the inner circuitry does not use the given DC supply voltage as is. Many different circuits use different voltage levels optimized for their specific functions. It is not uncommon to encounter that even some individual integrated circuits (ICs) might require different supply voltages for different circuits within them. Therefore the need for converting the supply voltage level to other needed different voltage levels required by the following circuits. This is where power converter circuits and topologies come into the picture.
These bus voltage DC-DC converters can be designed to perform many dif-ferent tasks depending on the application and system specifications. They can be isolated or non-isolated; regulated or unregulated; up converter or step-down converters. There could also be protection features such as over current,
converter design depending on the system needs. However each integrated fea-ture increases the overall cost, size and complexity of the design. There are many varieties of converter topologies where given a unique application usually a spe-cific topology is more suitable than the others. Choosing the right topology for the application can save the designer money, time and effort.
In applications such as portable electronics, mobile devices, sensory circuits, digital clocked circuits and wireless systems power requirements are typically strict. Many of such systems employ batteries where voltage levels are mostly around 5 Volts or less due to both current battery technology. In such applications higher voltages than the battery voltage might be needed, which would make the use of step-up converters necessary. Step-up converters can be divided into two main categories which are: inductor based converters and inductorless converters. Inductor based converters use an inductor to store and deliver energy to produce higher voltages than the input supply. Such converters can also use transformers to provide isolation where it is needed. Simplest topology of an inductor based non-isolated step-up converter is a boost converter which is seen in Figure 1.1.
+
−
LOADFigure 1.1: Boost Converter Topology
Simple boost converter is useful in applications where a medium to moderately high power is needed by the load. However for light to very light loads, the use of a boost converter becomes more and more disadvantageous due to the size and cost of an inductor which is a bulky component. Very low power step-up converter applications are quite common in most circuit boards such as: high side NMOS switching of half bridge topologies, high side static NMOS gate drive circuits, low
be cheaper, simpler and easier solutions than inductor based converters.
Inductorless step-up converters also use a switching element to control the power transfer, however instead of using an inductor as a charge storage element, these topologies use capacitors. A commonly used example could be given as a simple bootstrap circuit which is used in NMOS based switching bridge topolo-gies. In such circuits the high side NMOS requires a drive voltage at its gate which is higher than the bus voltage. That higher voltage is generated by the use of a bootstrap circuit where a capacitor and a diode is utilized to generate a floating power supply for the high side drive circuitry which can be seen in Figure 1.2. The circuit charges the bootstrap capacitor to the internal supply voltage through the diode when the low side MOSFET is turned on. When the drive circuitry turns off the low side MOSFET, and starts turning on the high side MOSFET the diode turns off and the capacitor acts as a floating power supply.
Vdd
INTERNAL SUPPLY
For example a high side NMOS transistor is commonly used for inrush limiting and input voltage-current protection applications [2, 3]. An example hot swap control circuitry is shown in Figure 1.3. Hot swap control allows designers to protect the system from high inrush currents, short circuits and potential load failures affecting the system power rail. In such applications the MOSFET, in steady state, is either fully on or fully off. To turn the MOSFET fully on, there still is the need for a gate voltage higher than the bus voltage. Since there is not a switching node, bootstrapping cannot be easily implemented. Almost all high side static NMOS transistor control ICs in the market today solves this issue by using a voltage step up topology called: Charge Pumps (CPs) [4, 5, 6].
NMOS R1 R Vout Vin Hot Swap Controller
Figure 1.3: High Side Hot Swap Con-troller
A charge pump is a capacitor based switching converter which converts an input voltage to a different voltage level by pumping charges through capacitors to generate a desired output voltage. Output voltage of a charge pump circuit can be negative, positive, higher or lower than the input voltage. Several commonly used charge pump topologies and their working principles are explained in detail in Chapter 2.
In this presented work a charge pump topology was implemented on a silicon chip
manufactured with 0.35µm CMOS process to function as a bias circuitry for a
capacitive load. The charge pump based bias circuits and required timing control circuits are designed. Main objective was to have a step-up circuit which works with 5 Volts supply and boosts it up to 15 Volts, then after some configurable time the converter reduces the output voltage to 12 Volts and keep it at that level indefinitely.
The intended load of the circuit is a capacitive load which, ideally, would have very small amounts of leakage currents. Therefore the designed converter can have a very low output power capability. This allowed us to use smaller pump capacitors and therefore to have a smaller circuit on the silicon die.
CMOS inverter based ring oscillators were used for generating the switching clock signals. Different timing circuitry designs were implemented to provide the time delay after which the converter reduces the output voltage slightly. Timing circuitry was used together with a control circuit which effectively disabled several stages of the charge pump converter.
Overall, the designed circuitry can be used as a proof of concept for our require-ments and with several adjustrequire-ments it can be adapted to different applications requiring simple timing and voltage step-up solutions.
1.3
Thesis Outline
Chapter 2 provides an overview of charge pump topologies, important figures of merits, working principles and a literature summary of those topologies. Chapter 3 gives the design specifications of this work, and explains the circuit blocks in
and compares the results with post-layout SPICE simulations and these results are examined to draw conclusions for improving future designs.
Chapter 2
Overview of Charge Pump
Topologies
CPs can easily be built with discrete components without taking up much space on the circuit board due to low power requirements. High voltages can be gener-ated on a board to supply power to different chips and parts of the system. Due to the switching nature of CP converters, in noise sensitive applications a low dropout linear regulator can be used to filter high frequency noise of the CP.
Charge Pumps are not necessarily always built with discrete components. Since parallel plate capacitors are compatible with planar CMOS technology of today, such converters can be integrated directly into silicon chips. Such integrated charge pump circuits can be used for many different applications and purposes inside the IC and on the circuit board as well.
The current trend in miniaturizing CMOS circuits and reducing power con-sumptions caused a reduction in MOSFET threshold voltages as well as operating supply levels. However many parts of ICs might still need high voltages to oper-ate, such as MEMS devices, EPROM programmers and power switches [7, 8, 9].
chip integrated CPs also find uses in areas such as energy harvesting circuits, subthreshold voltage reference generation, voltage inverter, fast NMOS based LDOs and system on chip applications [10, 11]. The integration of this multi-functional circuit allows for more compact, more optimized and simpler designs for electrical engineers and IC manufacturers.
Simplest form of voltage amplification circuitry was Greinacher voltage dou-bler, and it was proposed by Heinrich Greinacher [12]. The circuit was composed of a clamp circuit followed by a peak holder which is shown in Figure 2.1. The operation principle was that an AC input voltage was clamped by a clamp diode which forced the clamp capacitor to charge up to a DC voltage level of peak input voltage. Therefore the clamp node would be the DC offset version of the input voltage with double the peak voltage. The output peak holder circuit simply rectifies this signal to achieve a DC voltage at the output where the DC value was double the input peak voltage.
D6 D C7C D7D C22 C Vin Vout Hot Swap Controller Voltage
Clamper PeakHolder
Figure 2.1: Greinacher Voltage Doubler
First commonly used charge pump topology was proposed by Dickson in 1976 [13]. This circuit was presented as an improvement over an older proposed charge pump topology by Cockcroft and Walton [14]. Cockcroft & Walton multiplier was used in 1930s to generate megavolts and kilovolts of voltage levels from lower AC or DC voltages. Such voltage levels were specifically used in particle accelerators and nuclear energy research. The inventors of this topology received the Nobel Prize in physics for their work on nuclear experiments with accelerated particles [15]. The circuit, shown in Figure 2.2, was utilizing capacitors and
side capacitors C1 and C3 capacitors are working together with D1 and D3 to clamp the AC input signal to the anode voltage of the respective diodes. Anode of D1 is at ground, therefore C1 charges up to a DC voltage to offset the input signal up. Then D2 and C2 acts as a peak holder circuit to charge C2 to double the peak input voltage. This pushes the anode voltage of D3 upwards which in return clamps the cathode voltage to two times the input peak voltage. This consecutive voltage boosting results in significantly higher voltages at the output.
D22 D1 D23 D4 C23 C3 C24 C1 C25 C3 D24 D2 D25 D3 C26 C4 Vin Vout
Figure 2.2: Cockcroft & Walton Voltage Converter
Cockcroft & Walton converter allowed each capacitor to charge up to twice the input peak voltage value. This property of the converter allowed designers to use capacitors with lower voltage ratings than the expected output voltage. Reduced stress also made using smaller components possible. However this topology had several shortcomings as well. For this topology to have high conversion ratios, the stray capacitances had to be much smaller than pumping capacitors. Therefore large capacitor values were required which made implementing this topology on a silicon die harder. Moreover, as the number of stages increased the output impedance of this circuit also increased due to serially connected capacitors in the power path. Thus, achieving high output currents became more challenging as more stages were cascaded. To overcome these shortcomings and to have a more reasonable monolithic voltage step up converter, Dickson proposed his topology.
clock signals which usually have amplitudes same as the input voltage amplitude. Main operational difference of Dickson charge pump compared to Cockcroft & Walton converter is that it does not use a time varying input voltage but instead uses clock signals to gradually pump charges across diodes. The operation prin-ciple of this topology is explained more in detail in Chapter 3. This topology offered less sensitivity to stray capacitances, lower output impedances and higher output currents thus making the use of smaller capacitors possible. This allowed designers to successfully implement this topology on integrated circuits. Dickson charge pump’s main challenge is that as the number of stages increase to have a larger output voltage, the capacitor voltage stresses also increase. The last ca-pacitor of the cascaded topology has to endure the full range of output voltages. Moreover due to this voltage increase at each cascaded node, if the diodes are implemented by using diode connected NMOS transistors, due to the body effect the loss of each stage increases. An improved version of Dickson’s topology was proposed as the bootstrapped Dickson charge pump.
D C27 C D C D28 D C D C D C D31 D C D C33 C D33 D C34 CLoad Vin Vout ϕ1 ϕ2
Figure 2.3: Dickson Charge Pump
The body effect induced threshold voltage shift problem of classical Dickson charge pumps were solved by the introduction of bootstrapped Dickson charge pumps [16, 17]. In this topology a bootstrap MOSFET drive circuitry is built around each stage to use the MOSFETs in their triode region. The bootstrap circuit is shown in Figure 2.4. During the time interval where a transfer switch is OFF, the bootstrap circuitry charges a capacitor to supply voltage. When the clock phase changes, the bootstrap circuitry connects this charged bootstrap ca-pacitance across the transfer switch’s gate and drain terminals as shown in Figure
quired voltage gain, less number of stages can be used compared to the Dickson Charge Pump. However a tradeoff has to be made and taken into account since the bootstrapped topology comes with increased complexity, increased number of clock signals and extra circuitry. This topology is especially useful for applica-tions where the input voltage supply is low and therefore diode forward voltage losses start to dominate.
M 1 P M O S M 3 N M O S M4 M 5 N M O S C35 Cb M6 NMOS M 2 N M O S C36 C M 7 P M O S M 8 N M O S M9 M 1 0 N M O S C38 Cb NMOS M 1 2 N M O S C39 C CLoad M 1 3 P M O S M15 C37 Cb M17 NMOS V in ϕ1 ϕ 1 ϕ 1 ϕ 1 ϕ 2 V in ϕ2 ϕ 2 ϕ 2 ϕ 2 ϕ 1 V in ϕ2 ϕ 2 ϕ 2 ϕ 2 Vin Vout
Figure 2.4: Bootstrapped Dickson Charge Pump
D S D S
Vs = Vd-Vth Vs = Vd
(a) (b)
Figure 2.5: Transfer switch in ON state. a) Dickson Charge Pump, b) Bootstrapped Dickson Charge Pump
Another variant of bootstrapped Dickson Charge Pump is shown in Figure 2.6. This topology uses boost transistors and additional clock control signals to
on boost transistor shorts the gate and source of the transfer switch TN, at the same time charges the boost capacitor CBN to the node voltage. Then boost control signal connected to CBN+1 becomes high, boosting the gate voltage of TN+1 through previously charged CBN+1. This turns the TN+1 fully ON and reduces transfer losses. Although different bootstrap topologies exist, the aim of remains the same which is solving the threshold voltage loss of Dickson Charge Pump. NMOS1 NMOS2 C41 Cb C42 C NMOS3 NMOS4 C43 Cb C44 C NMOS5 NMOS6 C45 Cb C46 C NMOS7 NMOS8 C47 Cb C48 C NMOS9 C49 CLoad ϕ 2 ϕ 1 ϕ 2 ϕ 1 Vout Vin ϕ b 1 ϕ b 2 ϕ b 1 ϕ b 2 ϕ1 ϕ2 ϕb1 ϕb2
Figure 2.6: Boosted Charge Pump
Another improved topology derived from regular charge pumps was the double charge pump topology [19]. This topology uses two parallel connected regular charge pump circuits as seen in Figure 2.7. The pump capacitances are reduced in half to keep the total pump capacitance the same. Again two out of phase clocks are used to drive the pump capacitors, however the difference is that the at each half cycle of a clock, only one of the two parallel charge pump circuits charge
output ripple frequency seen by the output capacitor. Output voltage and gain per stage are not affected by the use of this topology.
D34
D
C50
C
D35
D
C51
C
D36
D
C52
C
D37
D
C53
C
D38
D
C
D39
D
C57
CLoad
D42
D
C58
C
D43
D
C59
C
D44
D
C60
C
D45
D
C61
C
D46
D
C62
C
D47
D
Vin
Vout
ϕ1
ϕ2
Vin
ϕ2
ϕ1
Figure 2.7: Double Charge Pump Topology
Another variety of charge pump topologies can be named as series-parallel charge pumps. This topology, as the name implies, connects charge pump capac-itors in parallel and in series periodically as it can be seen in Figure 2.8 [20, 21]. At the first half of the period the pump capacitors are charged to the input volt-age, then all the pump capacitors are connected in series by switches. Thus a voltage gain of N is achieved, where N is the number of pump capacitors. This topology has the disadvantage of having large inrush currents due to simultaneous charging of pump capacitors in parallel. This can induce unwanted stresses in the circuit and to the supply. To overcome this problem a circuit was proposed by Hara et al [22]. The proposed circuit utilized a network of switches and diodes to achieve a timing in which individual pump capacitors are charged one by one. This would reduce the input inrush current greatly by reducing the capacitive loading.
C55 C C56 C C63 C C64 CLoad Vin Vout ϕ1 ϕ2 ϕ1 ϕ1 ϕ2 ϕ1 ϕ1 ϕ2 ϕ1 ϕ1 ϕ2
Figure 2.8: Series-Parallel Charge Pump Topology
In some applications several different output voltages might be needed in dif-ferent time intervals. Such ICs might benefit from using an adaptive charge pump topology where the effective number of stages of the charge pump can be changed during the circuit operation by controlling its driving clock signals and phases
of those clocks in relative to one another [23, 1]. Adaptive control provides
flexibility to the designer and allows the circuit to operate at an optimum opera-tion point for a given load and desired output voltage. An example circuit of an adaptive charge pump which can act as a pump with 1, 2 or 3 stages is shown in Figure 2.9. The circuit always uses the same total capacitance to pump charges, therefore it uses silicon area efficiently.
D40 D D41 D D48 D D49 D C C66 C D50 D D51 D D52 D D53 D D54 D C67 C C68 C D55 D D56 D D57 D D58 D D59 D C69 C C70 C D60 D D61 D D62 D C71 CLoad F1 F2 F3 F4 F5 F6 Vout Vin
Chapter 3
Design and Simulation
In this chapter the design requirements are laid out and the Dickson Charge Pump topology is explained in detail. Then sub-circuit blocks used in the design are shown. Their working principles are explained and schematics are given. Designed layout figures are provided as well as post-layout simulations which verify the expected operation of the circuits.
These sub-circuit blocks are used together in a way to create several main circuit blocks. Those main blocks are also explained, their schematics, layouts
and post-layout simulations are provided. All the simulations are done with
Spectre.
3.1
Design Specifications
The bias signal needed by the expected load is basically a DC voltage which is generated by the 5 Volts supply rail. 15 Volts bias has to be achieved and kept constant for some undetermined amount of time, after which the bias voltage should reduce to 12 Volts. The desired output voltage waveform is shown in Figure 3.1.
Time (s) 0 1 2 3 4 5 6 7 8 9 10 Vout (V) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 3.1: Desired Output Voltage Waveform
Moreover, it was required that the circuitry should not need any external control or trigger signals to operate. Therefore any necessary control signals, clocks and triggers should be generated internally.
The expected load of this circuit is of capacitive nature, thus DC current loading is expected to be minimal.
These requirements were satisfied in this thesis by using PMOS based Dick-son Charge Pumps. Clock signals were generated internally with ring oscillators. Delay timing required for the output voltage reduction was achieved with three different approaches: External capacitor programmed delay, Surface leakage cur-rent based delay, OFF PMOS curcur-rent based delay. Following sections explain these circuits in detail.
3.2
Detailed Analysis of Dickson Charge Pump
In this thesis, charge pump circuits were derived from the classical Dickson Charge Pump topology [13]. Therefore prior to going into detail of the designed blocks, it is needed to understand the operation principles behind Dickson’s topology. The
circuit including stray capacitors CS and pump capacitors C is given in Figure
3.2. Charge transfer devices are shown as diodes.
D63
D
C72
C
D64
D
C73
C
D65
D
C74
C
D66
D
C75
C
D67
D
C76
C
D68
D
C77
C
D69
D
C78
C
D70
D
C79
CLoad
C80
Cs
C81
Cs
C82
Cs
C83
Cs
C84
Cs
C85
Cs
C86
Cs
Vin
Vout
ϕ1
ϕ2
Figure 3.2: Dickson Charge Pump with Stray Capacitances
In the given circuit, Φ1 and Φ2 are two out of phase clock signals with ampli-tude equal to the supply voltage as shown in Figure 3.3. Vin is the input voltage which is usually tied directly to the available voltage supply.
ϕ1
ϕ2
In order to derive the output voltage, the voltage difference between two cas-caded stages VN-VN-1should be calculated where N corresponds to stage number.
Nodes between stages are numbered as it is shown in Figure 3.4.
D
C87
C
D72
D
C88
C
D73
D
C89
C
D74
D
C90
C
C91
C
D75
D
C92
C
D76
D
C93
CLoad
Vin
ϕ1
ϕ2
Vout
. . .
. . .
1
2
3
N-1
N
Figure 3.4: Dickson Charge Pump Node Numbering
First, an expression of voltage gain per stage is derived under the assumption
of steady state operation and zero output current. In steady state, no load
condition diodes no longer transfer charges across stages since there is no load and all the capacitors are assumed to be fully charged. Voltage difference between two consecutive stages can be calculated using the Equation 3.1 where V’Φ is the
voltage variation due to the clock signal driving Nth node and VD is the forward
diode voltage.
VN− VN-1 = V0Φ− VD (3.1)
Due to steady state analysis, V’Φ can easily be calculated by ignoring the
charge transfer diode. Thus, during the pumping phase the Nth stage becomes the equivalent circuit shown in Figure 3.5.
NMOS
Cs
C
ϕ
ϕ
VN
Figure 3.5: Dickson Charge Pump Node Pumping Phase
During the pumping phase, the pumped charge ∆Q is stored equally in both
capacitors. Assuming the clock amplitude is VΦ then the overall voltage change
across two capacitors is VΦ. This change is equal to the individual voltage changes
across both capacitors ∆VCand ∆VCSwhich are the voltage changes across pump
capacitor and stray capacitor respectively. Naming the voltage increase at the node due to the pumping clock as V’Φ, the following equations are derived.
∆ VC = ∆ Q C , (3.2) ∆ VCS = ∆ Q CS , (3.3) VΦ = ∆ VC+ ∆ VCS = ∆ Q C + ∆ Q CS , (3.4) ∆ Q = VΦ× ( 1 C + 1 CS), (3.5) V0Φ = ∆ VCS = ∆ Q CS , (3.6) V0 = V × ( C ). (3.7)
tance increases, the voltage seen at the pumping node due to the pumping clock decreases. Second, in an ideal circuit where there is no or negligible stray capac-itance; the node voltage would see a voltage swing equal to the clock amplitude. Using Equation 3.7 and 3.1, the Equation 3.8 is derived for one stage gain of a zero output current Dickson charge pump.
VN− VN-1= VΦ× (
C
C + CS) − VD (3.8)
The results so far were under the zero output current assumption, however a charge pump exists so that it can provide some current to a designated load. Therefore the analysis has to be extended for a loaded case where the load current is IO. Steady state assumption still holds and does not change the final DC results.
Let the clock frequency be fΦ and the clock period be TΦ. Once every period
some charge will be pumped from each stage to the output. When there is no load current, this charge becomes zero at steady state. However when there is load current, in order to keep the output voltage level constant, the output capacitor has to be supplied the charge equivalent of the load’s charge consumption. During a switching period, the charge consumed by the load can be calculated using Equation 3.9.
QOut= IO× TΦ=
IO
fΦ
(3.9)
This constant charge has to come from each charge pump stage since they are serially connected. Thus an output current will load every stage equally. The node voltage reduction can be calculated using the following equations where
∆QS is the charge coming from stray capacitance, ∆QC is the charge coming
from pump capacitance and ∆VL is the node voltage reduction due to output
∆ QS = CS × ∆ VL, (3.10) ∆ QC= C × ∆ VL, (3.11) ∆ QS+ ∆ QC = QOut = (C + CS) × ∆ VL. (3.12) ∆ VL = IO fΦ× (C + CS) . (3.13)
Combining the previous results using Equations 3.8 and 3.13 the Equation 3.14 is derived. VN− VN-1 = VΦ× ( C C + CS) − VD− IO fΦ× (C + CS) (3.14)
The result in Equation 3.14 is given for a gain of one stage. To derive the total output voltage, this result has to be generalized to an N stage Dickson Charge
Pump with Vin input voltage. The voltage gain of N cascaded stages ∆VNstage
would be equal to:
∆ VNstage = N × [VΦ× ( C C + CS) − VD− IO fΦ× (C + CS) ] − VD
The additional VD loss comes from the output diode. This expression gives the
voltage gain from input to output, thus the output voltage Vout can be calculated
using the input voltage and derived equations as follows:
Vout = V in + N × [VΦ× ( C C + CS) − VD− IO fΦ× (C + CS) ] − VD (3.15)
The derived equation assumes a constant output voltage, however under load-ing, the output voltage will deviate around its DC average value. This output ripple is due to the fact that during half of the switching period, the output ca-pacitor is disconnected from the charge pump circuit and is supplying the load current all by itself. This causes a voltage drop at the output which is named
CO during the half cycle of the switching period Tφ: Qripple= IO× ( Tφ 2 ), (3.16) Vripple= Qripple× 1 CO = IO× ( Tφ 2 ) × 1 CO . (3.17)
Thus, Dickson Charge Pump topology’s voltage gain and output ripple proper-ties are analyzed and several important conclusions can be made. Using Equation 3.14 it can be concluded that the voltage amplification prevails as long as the con-dition given in Equation 3.18 is satisfied. This equation summarizes the fact that to have a higher current capacity, the circuit has to have larger pump capacitors in order to maintain its gain. Moreover, smaller stray capacitances correspond to larger gain. Also the switching frequency appears to be an important parameter which can be increased to reduce the pump capacitor sized without changing the output voltage. This result appears to be similar to what it widely known from power electronics where the passive filter and magnetic component sizes tend to become smaller as the switching frequency increases. Furthermore, higher switch-ing frequency also results in lower output voltage ripple as seen in Equation 3.17.
VΦ× ( C C + CS) − VD− IO fΦ× (C + CS) > 0 (3.18)
Up to this point the transfer switch element of the Dickson Charge Pump was assumed to be a normal diode. However usually this diode is created with a diode connected NMOS transistor as shown in Figure 3.6. Gate and Drain terminals of the NMOS device are connected together forcing the device to work under saturation. When a voltage is applied to the Drain terminal, the transistor turns ON after the difference between its gate and source terminals exceed its
VS = VD− VTH (3.19)
D77
D
D
G
S
D
S
Figure 3.6: Diode Connected NMOS Transistor
Clearly the Equation 3.19 can be modeled as a diode with forward voltage
drop of VTH. Therefore it is necessary to examine the threshold voltage of an
NMOS enhancement transistor which is given in Equation 3.20 [24].
VT H = VT 0+ √ 2qSiNA COX (p2ΦF + VSB − p 2ΦF) (3.20) Where;
VSB: Source to body voltage,
VT0: Threshold voltage when VSB is zero,
ΦF: Fermi potential,
Si: Permittivity of Silicon,
NA: Acceptor doping density,
q: Charge of an electron,
COX: Gate oxide capacitance per unit area.
Equation 3.14. Therefore when NMOS devices are used as transfer elements,
as the stage number increases, the VSB also increases. This in return increases
the threshold voltage of the transistor thus increasing the loss component given
as VD in Equation 3.14. For these reasons when using diode connected NMOS
devices, the body effect and the threshold voltage increase has to be taken into account and in fact after enough number of stages, the voltage gain per stage might become negative due to large threshold voltages.
To conclude, Dickson Charge Pump topology’s main operating principles are explained and several expressions were derived for voltage gain, voltage ripple, threshold voltage shift due to body effect. This thesis’s work is different than the general Dickson topology in which PMOS diode elements were used to negate the body effect threshold voltage shift of NMOS devices. Moreover grounded input voltages was used in charge pump circuits to enable integration of several timing control and trigger circuits. Following section explains the designed sub-circuit blocks and continues with final main circuits.
3.3
Sub-Circuit Blocks
In this section sub-circuit blocks are described in detail and their layouts are shown. Furthermore, post-layout SPICE simulations are given. The design used in this work uses the 350 nm AMS process with four metal and two polysilicon layers.
3.3.1
CMOS Inverter for Ring Oscillator
As it was explained in Section 3.2, a Dickson Charge Pump uses two out of phase clock signals to drive pumping capacitors. In this work a ring oscillator
which results in an astable operation where the output oscillates.
The basic block of the oscillator is a CMOS inverter with a capacitive load at the output as shown in Figure 3.7. 500nm, 5 Volts compatible transistors are used
and widths are chosen as 1.0µm for top PMOS and 0.8 µm for bottom NMOS
transistor.
Capacitive load of 100fF is connected at the output of the inverter to increase the delay time from input to output. This increase of the delay translates into a reduction in the clock frequency of the ring oscillator as it is explained in Subsection 3.4.1.
Cpoly
100fF
VDD
IN
OUT
W=0.8µm
L=0.5µm
W=1.0µm
L=0.5µm
Figure 3.7: 1-Stage Inverter with Capacitive Load Circuit
The layout of the circuit is shown in Figure 3.8. The 100fF output delay capacitor is realized by using parallel plate polysilicon capacitor. The layout
Post-layout parameters were extracted and the circuit was simulated using Spectre. Transfer characteristics of this inverter circuit is shown in Figure 3.9.
Input Voltage (V) 0 1 2 3 4 5 Output Voltage (V) 0 1 2 3 4 5
Figure 3.9: 1-Stage Inverter with Capacitive Load Transfer Characteristics Post-Layout Simulation
3.3.2
1-Stage Charge Pump Block
Transfer switches of the designed circuit are based on the body diodes of PMOS transistors. PMOS devices are selected so that all the devices have separate body connections with possibly different voltage levels. This allowed us to alleviate the body bias threshold voltage shift problem linked to NMOS devices.
Available capacitor types of the manufacturer’s CMOS process are examined. It is understood that in order to achieve a high pumping capacitance a high capacitance per unit area is needed. There were three seemingly appropriate options which are gate capacitances of 3.3V and 5V MOSFETs as well as Poly1-Poly2 capacitance. Another constraint when selecting the right capacitor is the breakdown voltage characteristic of the capacitor. In the Dickson charge pump topology, the capacitors will be facing higher and higher voltage stresses as the stage numbers increase. The pump capacitor of the last stage will undergo a stress voltage equal to the value of the expected output. The breakdown voltages
whereas the breakdown voltage of Poly1-Poly2 capacitor is given as 30 Volts. Therefore Poly1-Poly2 capacitor is chosen.
300fF polysilicon capacitors are used as charge pump capacitors. Maximum voltage stress expected by the pump capacitors is simply the maximum output voltage value. In the used CMOS process the breakdown voltage of pump capac-itors was 30 Volts, therefore the expected maximum output voltage value of 15 Volts does not exceed the tolerance levels of these capacitors. Since the expected load of the circuit is of capacitive nature, the transfer devices will not endure high DC currents. If an application was to require higher DC output currents then wider transfer devices has to be used.
Body, source and gate connections of PMOS transistor devices were shorted, leaving the body diode available for conduction whenever the drain voltage be-comes higher than the source voltage. Maximum reverse voltage stress seen by the devices are 5 Volts, which is the ideal maximum pump voltage increase from one stage to the next. As the number of stages increase, the body voltage of PMOS devices also increase. This causes a Body to Substrate reverse voltage stress and its maximum value is equal to the expected maximum output voltage value of 15 Volts. This does not exceed the 32 Volts N-well to substrate threshold limit specified by the manufacturer.
The primary building block of the charge pumps is shown in Figure 3.10. Three terminals of the block are identified as CLK, Vhigh and Vlow. CLK is the charge pumping clock signal which is the output of a ring oscillator. Vlow is the low voltage side of the device, anode of the body diode. Vhigh is the high voltage side of the device, cathode of the body diode. The charge pump cell transfers charges from Vlow side to the Vhigh side whenever the CLK signal is low and there is a higher voltage at the Vlow side.
Cpoly
300fF
C
LK
Vhigh
Vlow
W=1.0µm
L=0.5µm
Figure 3.10: 1-Stage Charge Pump Circuit
The layout of 1-stage pump is given in Figure 3.11. The layout dimensions are
Since the transfer devices of the circuit are operated as diodes, at each stage, there will be a diode forward voltage drop. It is important to characterize this voltage drop to correctly estimate the needed number of stages for a given appli-cation. A post-layout simulation on extracted parameters was done to accurately show this diode voltage drop. The test circuit and the result is shown in Figure 3.12. The observed voltage drop of 0.8 Volts is in agreement with the manufac-turer specifications.
5V 100k Cpoly 300fF Vin Vout W=1.0µm L=0.5µm Vin (V) 0 1 2 3 4 5 Vout (V) 0 1 2 3 4 5
(a) Test Circuit (b) Post-Layout Simulation Result
Figure 3.12: 1-Stage Charge Pump Diode Characteristics Post-Layout Simulation
3.3.3
Capacitive Timer Block
To achieve output voltage reduction after a certain amount of time, the circuit has to include timing circuits. One of the simplest and commonly used timing circuits is of course an R-C timer. A capacitive timer block was designed to serve as a time trigger control circuitry. The schematic is shown in Figure 3.13. Apart from supply and ground connections, there are three terminals of this block: Ctimer, Turn OFF Delay and Turn On Delay. Ctimer is a terminal connected to a pad of the manufactured chip where it can be accessed externally. An external capacitor connected between this pad and ground allows the user to program the delay time by selecting an appropriately sized delay capacitor. The time constant of the circuit is based on the connected capacitor value, internal resistor of 6.66 kΩ and the inverter threshold.
M10 M11 PMOS M12 M13 PMOS M14 M15 PMOS Rpoly 6.66k VDD Ctimer Turn_On_Delay Turn_OFF_Delay W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm
Figure 3.13: Capacitive Delay Timer Circuit
The operation of the circuit begins with the power up of the IC. Following the power up, the externally connected timing capacitor begins to charge up towards 5 Volts. When the voltage across the capacitor is lower than the VIH of the input
inverter, the input inverter output voltage stays at 5 Volts. It follows that the Turn On Delay voltage is LOW and Turn OFF Delay voltage is HIGH. When the capacitor charges above the VIH, the input inverter changes state and other
inverters follows as well. Thus after a time, determined by the capacitor value and internal circuit parameters, the Turn On Delay voltage becomes HIGH and Turn OFF Delay voltage becomes low. These voltages can be used to trigger any circuitry of choice.
At a given time t1, the voltage of the capacitor is given by Equation 3.21.
Assuming that the initial capacitor voltage is zero then the trigger delay time tdelay can be calculated using Equation 3.22. Using these equations the capacitor
value for the desired delay time can be calculated where VC, VIH and VDD are
capacitor voltage, inverter input high threshold and supply voltage respectively.
VC = V DD × (1 − e−t1/RC) (3.21)
layout dimensions are 26.25µm x 15.25 µm.
Figure 3.14: Capacitive Delay Timer Circuit Layout
In order to verify the timing controllability of the designed capacitive timer block, post-layout simulations were performed using extracted parameters. Two different cases were simulated using Spectre with two different standard valued timing capacitor values: 100nF and 1000nF. The resulting output signal wave-forms are shown in Figure 3.15. 100nF capacitor resulted in 0.3ms delay whereas 1000nF capacitor resulted in 3ms delay. This is expected due to the increased time constant of the circuit as the capacitor value increases
Time (ms) 0 0.2 0.4 0.6 0.8 1 Output Voltage (V) 0 1 2 3 4 Turn ON Delay Time (ms) 0 2 4 6 8 10 Output Voltage (V) 0 1 2 3 4 Turn ON Delay
(a) 100nF Delay Capacitor (b) 1000nF Delay Capacitor
Figure 3.15: Capacitive Delay Timer Circuit Post-Layout Simulation
Using Equation 3.22 and the results of Figure 3.15, VIH is extracted to be
1.81 Volts. For the circuit given in Figure 3.13, using Equation 3.22 the external capacitor value vs trigger delay graph is plotted as shown in Figure 3.16.
Delay Time (s) 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
3.3.4
Leakage Delay Block
The capacitive timer block which is explained in the previous subsection uses an internal resistor and an external capacitor to delay the triggering event. Another approach was shaped which uses both R and C components internally. This could have been achieved straight forwardly however in order to have long enough time delays the needed component values increase. This causes enlargement of the circuit area which is not desired. Thus, instead of using a determined value for a resistor we chose to use surface leakage path as a resistor.
Surface leakage properties of a chip mainly depends on the manufacturing process and the impurities in the environment. Therefore it is not possible to estimate the value of surface leakage, however in the past it was observed in our research group that such leakage paths exist and they can in fact charge MOSFET gate capacitances and turn floating gate MOSFETs ON. The circuit model is given in Figure 3.17.
The operation principle is exactly the same as the capacitive delay block. In leakage delay block, a 784fF polysilicon capacitor is used as the delay capacitor and according to the Equation 3.22 a delay will occur.
M16 NMOS M17 PMOS M18 NMOS M19 PMOS M20 NMOS M21 PMOS Cpoly 784fF RSurface VDD Turn_On_Delay Turn_OFF_Delay W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm
Figure 3.17: Leakage Delay Timer Circuit
The layout of this circuit is given in Figure 3.18. The surface leakage path is created using closely deposited metal paths on the same layer. The leakage paths
2
dimensions are 60.75µm x 36.55 µm.
Figure 3.18: Leakage Delay Timer Circuit Layout
3.3.5
Off-PMOS Delay Block
The third approach used in this work utilizes two OFF PMOS transistors as a leakage resistive path to delay the charging of an internal timing capacitor. The circuit is shown in Figure 3.19. Widths of the leakage MOSFETs are equally
chosen as 10µm to ensure the capacitor voltage settles at VDD
2 . M22 NMOS M23 PMOS M24 NMOS M25 PMOS M26 NMOS M27 PMOS Cpoly1 784fF M28 PMOS M29 PMOS VDD Turn_On_Delay Turn_OFF_Delay W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=10µm L=0.5µm W=10µm L=0.5µm
The layout of this circuit is given in Figure 3.20. The layout dimensions are
60.75µm x 36.55 µm.
Figure 3.20: OFF PMOS Delay Timer Circuit Layout
3.4
Main Circuit Blocks
This section describes the main circuit blocks designed in this thesis. These main blocks are created by combining the sub-circuit blocks explained in the Section 3.3.
3.4.1
11 Stage Ring Oscillator
Dickson Charge Pumps require two out of phase clock signals to drive the charge pump stages as explained in Section 3.2. In this work, these clock signals were generated using a ring oscillator. A ring oscillator is an astable oscillating circuit created by cascading an odd number of inverters and tying the output to the input.
to create the oscillator as shown in Figure 3.21. The inverters used in each stage are same and the one explained in subsection 3.3.1.
A2
A1
A3
A4
A5
A6
A7
A8
A9
A10 A11
11 Stage Ring Oscillator
Figure 3.21: 11 Stage Ring Oscillator Circuit
Each stage of the cascaded ring delays the signal for a certain time tinverter. For
N stages, the total delay at the output becomes N × tinverter. Then, the oscillation
frequency can be calculated using Equation 3.23.
foscillation =
1
2 × N × tinverter
(3.23)
The ring oscillator as shown in Figure 3.21 has a single clock output. In order to generate two out of phase clock signals, an output stage is required. This output stage will generate the clock signals to drive the pumping capacitors. Therefore this stage should be sized enough to handle the current draw needed by the pump capacitors. In this thesis a buffer circuit was designed with wide output transistors to provide enough current. The circuit consists of two parallel buffer legs where the bottom legs inverts the signal and the top leg inverts it twice to generate the same clock signal. This topology, shown in Figure 3.22, generates the necessary clock signals from the ring oscillator output.
M3 NMOS M4 PMOS M5 NMOS M6 PMOS M7 NMOS M8 PMOS VDD CLK VDD CLK_N CLK_P W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=1.6µm L=0.5µm W=2.0µm L=0.5µm W=1.6µm L=0.5µm W=2.0µm L=0.5µm
Figure 3.22: Ring Oscillator Output Stage Circuit
Ring oscillator is connected directly at the input of this output buffer circuitry. Since the ring drives two parallel inverters with high impedance inputs, the buffer stage will not load the oscillator and therefore will not interfere with its operation. The overall circuit is shown in Figure 3.23.
M84 M86
M88 NMOS
M89 PMOS
A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
VDD CLK VDD CLK_N CLK_P W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=1.6µm L=0.5µm W=2.0µm L=0.5µm W=1.6µm L=0.5µm W=2.0µm L=0.5µm 11 Stage Ring Oscillator
Figure 3.23: 11 Stage Ring Oscillator Circuit with Output Stage
Transient simulation with 1 MΩ load resistors at each output is carried out using extracted parameters and result is shown in Figure 3.24. As expected the CLK P is in phase with the input clock signal and CLK N is out of phase. These two clock signals are to be used as drive signals of the charge pumps in this work. The output clocks of the buffer have sharper edges compared to the input clock signal due to the increased drive capability of the output buffer’s wider transistors.
Time (ns) 10 20 30 40 50 60 70 80 90 100 Clock (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Clock Input CLK_P CLK_N
Figure 3.24: 11 Stage Ring Oscillator Transient Simulation with Output Stage
Ring oscillator layout is shown in Figure 3.25 which is basically 11 inverters,
which was shown in Figure 3.8, cascaded. The layout dimensions are 71µm x
The completed oscillator layout with output stage and two complementary
clock outputs is shown in Figure 3.26. The layout dimensions are 60.75µm x
Figure 3.26: 11 Stage Ring Oscillator with Output Stage Layout
Post-layout SPICE simulations of the ring oscillator is carried out using ex-tracted parameters. Resulting oscillating waveform is shown in Figure 3.27 where 11 Stage 100fF cascaded inverter ring oscillator generates 22 MHz square wave.
Time (ns) 10 20 30 40 50 60 70 80 90 100 Clock (V) 0 1 2 3 4
Figure 3.27: Ring Oscillator Post-Layout Simulation
3.4.2
Three Stage Charge Pump
A three stage charge pump circuit was designed using the charge pump blocks shown in Figure 3.10. The designed charge pump circuit is given in Figure 3.28. CLK N and CLK P signals are two out of phase clock signals which were gener-ated using the ring oscillator circuit shown in Figure 3.23.
Unlike the usual Dickson Charge Pump topology described in Section 3.2, the circuit in this work has a grounded input signal at the first stage. This clamps the first pumping stage voltage to above ground level. Using grounded input reduces the available output voltage level by an amount equal to the supply voltage. However by grounding the input, any intentional or unintentional grounding in the following stages do not short the supply thus providing additional design flexibility. This will be explained more in the following subsection.
Cpoly 300fF Cpoly 300fF Cpoly 300fF C1 CLoad C LK _ P Vout C LK _ N W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm
Figure 3.28: Three Stage Charge Pump Circuit
Layout of the three stage charge pump is shown in Figure 3.29. The layout
dimensions are 100µm x 75 µm. To provide a supply capacitance in order to
reduce the conducted noise, a 800 fF DC supply capacitor was also placed inside the layout.
Expected output voltage of an N stage charge pump can be calculated using the Equation 3.24 where Vforward is the diode forward voltage drop of each stage.
This equation differs from what was explained in Section 3.2 due to the grounded
input stage. The Vforward is calculated using Spectre in Subsection 3.3.2 to be
around 0.8 Volts. Thus using Equation 3.24 and taking Vdd as 5 Volts, N as 3 the output voltage can be calculated as 11.8 Volts.
Vout = N × V dd − (N + 1) × Vforward (3.24)
Spectre transient simulation is carried out. The output load is selected to be a 1pF capacitor and the supply voltage is ramped up from 0 Volts to 5 Volts. The
0 5 10 15 Output Voltage (V) 0 2 4 6 8 10 12 14
Figure 3.30: Threee Stage Charge Pump Transient Spice Simulation
3.4.3
Four Stage Charge Pump
A Four Stage charge pump circuit was designed using the charge pump blocks shown in Figure 3.10. The designed circuit is given in Figure 3.31. CLK N and CLK P signals are the driver clock signals which were generated using the ring oscillator circuit shown in Figure 3.23. Four stage charge pump provides the base of this thesis since the required output voltage levels around 15 Volts can be achieved with a Four Stage topology.
Cpoly 300fF Cpoly 300fF Cpoly 300fF CLoad Cpoly 300fF C LK _ P Vout C LK _ N W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µmL=0.5µm
Figure 3.31: Four Stage Charge Pump Circuit
Layout of the Four Stage charge pump is shown in Figure 3.32. The layout
dimensions are 100µm x 75 µm. To provide a supply capacitance in order to
reduce the conducted noise, a 300 fF DC supply capacitor was also placed inside the layout.
Figure 3.32: Four Stage Charge Pump Layout
Spectre simulation of the Four Stage Charge Pump is carried out. The output load is selected to be a 1pF capacitor and the supply voltage is ramped up from 0 Volts to 5 Volts. The resulting output voltage waveform is shown in Figure 3.33. The output voltage levels of 16 Volts is in agreement with the Equation 3.24.
0 5 10 15 Output Voltage (V) 0 2 4 6 8 10 12 14 16
Figure 3.33: Four Stage Charge Pump Spice Simulation
As explained in the Section 3.1, there is a need to reduce the output voltage some time after settling around 15 Volts. This problem was approached using three different circuits which are explained in the following subsection.
3.4.3.1 Delayed Output Voltage Reduction
The main voltage reduction approach employed in this work is basically reduc-ing the effective number of stages of the Four Stage charge pump circuit mid-operation. This is achieved by grounding the output of one of the first pump stage thus reducing the circuit into a Three Stage charge pump. In the general Dickson topology explained in the Section 3.2, this cannot be done because the input is connected to the power supply, thus any grounding of following stages would result in a shorting of the supply which is not desired.
con-when the control signal is asserted HIGH, the NMOS turns ON, shorting the first stage and reducing the effective number of stages by one.
This approach can be generalized to achieve different voltage levels and reduc-tion or increase mechanisms. For instance if the default control signal is HIGH, and after a delay it becomes LOW, then the output voltage increases. Control NMOS transistor is objected to a voltage stress increasing as the number of stages it can bypass increases. In this work at startup the control signal was designed to be LOW, thus Four Stage pump operates to generate 15 Volts from 5 Volts supply. After a delay the control signal is asserted HIGH, reducing the topology to Three Stage Pump and reducing the output voltage to 12 Volts as required.
M 4 0 Cpoly 300fF M 4 1 Cpoly 300fF M 4 2 Cpoly 300fF M 4 3 C3 CLoad M 4 4 Cpoly 300fF M45 NMOS C LK _ P Vout C LK _ N DELAY_CONTROL W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µmL=0.5µm W=0.8µm L=0.5µm
Figure 3.34: Output Voltage Reduction Control Circuit
The generation of the control signal DELAY CONTROL is accomplished using three different time delay circuitry which are explained as follows.
3.4.3.1.1 Delayed Output Voltage Reduction Using an External
First approach is based on the capacitive timer block explained in the sub-section 3.3.3. The capacitive timer block is connected to a Four Stage Charge Pump as shown in Figure 3.35 where the Turn On Delay output of the delay block is used as the DELAY CONTROL signal thus assuring a voltage reduction operation after a time delay.
The time delay expected by this topology can be calculated as shown in sub-section 3.3.3 using Equation 3.22.
PMOS NMOSM49 PMOS M50 NMOS Rpoly1 6.66k M 5 2 PMO S Cpoly 300fF M 5 3 PMO S Cpoly 300fF M 5 4 PMO S Cpoly 300fF M 5 5 PMO S C4 CLoad M 5 6 PMO S Cpoly 300fF M57 NMOS VDD Ctimer Turn_OFF_Delay C LK _ P Vout C LK _ N Turn_On_Delay W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µmL=0.5µm W=0.8µm L=0.5µm
Figure 3.35: Four Stage Charge Pump Circuit with Capacitor Programmable Output Voltage Reduction
Layout of the Four Stage charge pump with capacitive timer delay control
block is shown in Figure 3.36. The layout dimensions are 100µm x 94.3 µm. To
provide a supply capacitance in order to reduce the conducted noise, a 600 fF DC supply capacitor was also placed inside the layout.
Figure 3.36: Four Stage Charge Pump Layout with Capacitor Programmable Output Voltage Reduction
Transient simulation of the Four Stage Charge Pump with capacitive timer block is carried out on Spectre. The output load is selected to be a 1pF capacitor and the supply voltage is ramped up from 0 Volts to 5 Volts. The resulting output voltage waveform is shown in Figure 3.37. The output voltage levels of
15 Volts and 12 Volts are in agreement with the Equation 3.24. 18µs delay was
achieved using a 5nF external delay capacitor. This delay time can be increased or decreased using different values for the delay capacitor.
0 10 20 30 40 50 60 Output Voltage (V) 0 2 4 6 8 10 12 14
Figure 3.37: Four Stage Charge Pump Transient Simula-tion with 5nF External Delay Capacitor
3.4.3.1.2 Delayed Output Voltage Reduction Using an Surface
Leak-age Currents
Second approach used to generate the DELAY CONTROL signal is based on surface leakage block which is explained in subsection 3.3.4. Similar to what is done with the capacitive delay block, the circuit is connected to the Four Stage Charge Pump as shown in Figure 3.38. Expected time delay is dependent in
Rsurface, Cpoly and VIH as it was explained previously. The Turn On Delay
M 6 4 P M O S Cpoly 300fF M 6 5 P M O S Cpoly 300fF M 6 6 P M O S Cpoly 300fF M 6 7 P M O S C5 CLoad M 6 8 P M O S Cpoly 300fF M69 NMOS Cpoly 784fF RSurface C LK _ P Vout C LK _ N Turn_On_Delay VDD Turn_OFF_Delay W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µmL=0.5µm W=0.8µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm
Figure 3.38: Four Stage Charge Pump Circuit with Surface Leakage Delayed Output Voltage Reduction
Layout of the Four Stage charge pump with surface leakage timer delay control
block is shown in Figure 3.39. The layout dimensions are 102µm x 115 µm. To
provide a supply capacitance in order to reduce the conducted noise, a 600 fF DC supply capacitor was also placed inside the layout.
Reduction
3.4.3.1.3 Delayed Output Voltage Reduction Using OFF PMOS
based on OFF-PMOS Delay block which is explained in subsection 3.3.5. The circuit is connected to the Four Stage Charge Pump as shown in Figure 3.40. The Turn On Delay control signal is connected to the DELAY CONTROL pin to generate a voltage reduction after the time delay.
M 7 6 PMO S Cpoly 300fF M 7 7 PMO S Cpoly 300fF M 7 8 PMO S Cpoly 300fF M 7 9 PMO S C6 CLoad M 8 0 PMO S Cpoly 300fF M81 NMOS Cpoly2 784fF C LK _ P Vout C LK _ N Turn_On_Delay VDD Turn_OFF_Delay W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µm L=0.5µm W=1.0µmL=0.5µm W=0.8µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=0.8µm L=0.5µm W=1.0µm L=0.5µm W=10µm L=0.5µm W=10µm L=0.5µm
Figure 3.40: Four Stage Charge Pump Circuit with OFF PMOS Delayed Output Voltage Reduction
Layout of the Four Stage charge pump with OFF-PMOS timer delay control
block is shown in Figure 3.41. The layout dimensions are 102µm x 115 µm. To
provide a supply capacitance in order to reduce the conducted noise, a 600 fF DC supply capacitor was also placed inside the layout.
3.5
Post-Layout Simulations and Layout
Con-siderations
This section first provides the post-layout simulation results of the main circuit blocks then describes the final layout design considerations of the chip.
3.5.1
Post-Layout Simulations
Layout parasitics of the proposed main circuit blocks are extracted using Assura QRC tool in order to simulate the designed layout correctly with parasitics also taken into account.
Post-layout Spectre simulation with 1 MΩ load resistors at each output is carried out for 11 Stage Ring Oscillator with output stage using extracted pa-rameters. Two out of phase clock outputs with 25 MHz oscillation are shown in Figure 3.42. It appears that the designed layout does not hinder the operation of the oscillator circuitry.
Time (ns) 10 20 30 40 50 60 70 80 90 100 Clock (V) 0 1 2 3 4
Figure 3.42: 11 Stage Ring Oscillator Post-Layout Simula-tion with Output Stage
Three Stage charge pump layout parameters are extracted and simulated with 1pF output capacitor while the supply voltage is ramped up from 0 Volts to 5 Volts. The resulting output voltage waveform is shown in Figure 3.43. The extracted capacitive parasitics showed around 70 pF sized stray capacitances to ground from each pumping node. This in return caused a reduction in the output voltage in accordance with the formula given in Equation 3.15.
0 2 4 6 8 10 12 Output Voltage (V) 0 2 4 6 8 10
Figure 3.43: Three Stage Charge Pump Post-Layout Sim-ulation
Four Stage charge pump layout parameters are extracted and simulated with 1pF output capacitor while the supply voltage is ramped up from 0 Volts to 5 Volts. The resulting output voltage waveform is shown in Figure 3.44. Since the layouts of Three Stage and Four Stage charge pumps have the same pumping stages, the extracted capacitive parasitics were also the same which were around 70 pF sized stray capacitances to ground from each pumping node. This again showed itself as a reduction in the output voltage in accordance with the previous discussions.
![Figure 2.9: Adaptive Charge Pump Topology [1]](https://thumb-eu.123doks.com/thumbv2/9libnet/5666859.113366/28.918.304.663.169.780/figure-adaptive-charge-pump-topology.webp)
