LIST OF FIGURES

(1)

LIST OF FIGURES

Figure 1.1 Model of spread spectrum digital communication system 2

Figure 1.2 Spread Spectrum Encoding [6]. 4

Figure 1.3 The Illustrative example of CDMA [4]. 6

Figure 1.4 Multiplication of Channel with Chip1 [4]. 7

Figure 2.1 Source and channel coding. 8

Figure 2.2 A discrete transmission channel [9]. 10

Figure 2.3 Convolution encoder diagram [8]. 15

Figure 2.4 Feedback connection polynomials [8]. 16

Figure 2.5 Trellis description of a convolutional encoder [8]. 17

Figure 2.6 Soft decision decoding [8]. 19

Figure 3.1 Interleaving example [18]. 23

Figure 3.2 Structure of block interleaver of length L

π

= 12 25

Figure 3.3 Block interleaver example [18]. 27

Figure 3.4 Shift registration implementation of a convolutional

interleaver/deinterleaver [18]. 29

Figure 3.5 Convolutional interleaver/deinterleaver examples [18]. 30 Figure 4.1 Bit error probability for DS-SS with BPSK modulation over

an AWGN channel with E

b

/N

0

= 8.4 dB and with broadband

noise jamming of varying power. 36

Figure 4.2 Demodulator for DS-SS with BPSK modulation with rectangular chip

waveform. 37

Figure 4.3 Dispreading operation in the presence of narrowband jamming. 38 Figure 4.4 Bit error probability for BPSK-modulated DS-SS with

pulsed noise jamming with duty cycle ρ [23]. 41

Figure 4.5 Plot of (4.20) vs. E

b

/N

I

, parametric in γ, for E

b

/N

0

= 13 dB [23]. 42 Figure 4.6 Plot of (4.20) vs. E

b

/N

I

, parametric in γ, for E

b

/N

0

= 10 dB [23]. 43 Figure 5.1 Performance as a function of interleaver delay for random

and block interleavers [30]. 48

Figure 5.2 Block diagram of DS-SS communication system. 49 Figure 5.3 Performance of interleavers for convolutional encoded DS-SS

(Block length=400 bits, SNR=10 dB, jamming duty cycle ρ=0.5

and

E /b NJ

= SIR=0 – 6dB). 50

Figure 5.4 Performance of DS-SS system with and without interleaving and encoding.

(Block length=400 bits, SNR=10 dB, jamming duty cycle ρ=0.5

and

E /b NJ

= SIR=0 – 6dB). 51

viii

(2)

Figure 5.5 Performance of interleavers in convolutional encoded DS-SS for various block lengths, (SNR=10 dB, SIR=1dB, jamming duty cycle

^ ^⁰^.⁵

and block length=300-1400 bits). 52

Figure 5.6 Performance of DS-SS system with and without interleaving for

various block lengths (same parameters as in Figure 5.5). 52 Figure 5.7 Performance of interleavers in convolutional encoded DS-SS for various

block lengths, (SNR=10 dB, SIR=6 dB, jamming duty cycle

^ ^⁰^.⁵

and block length=300-1400 bits). 53

Figure 5.8 Performance of DS-SS system with and without interleaving for various

block lengths (same parameters as in Figure 5.7). 53 Figure C.1 The performance of interleavers with convolutional encoder for DS-SS

(Frame length=400 bits, SNR=10 dB, ρ=0.5 and SIR=0 – 6 dB). 71 Figure C.2 Performance of DS-SS system with and without interleaving and encoding.

(Block length=400 bits, SNR=10 dB, jamming duty cycle (ρ=0.5)

and

E /b NJ

= SIR=0 – 6 dB). 72

Figure C.3 Performance of interleavers in convolutional encoded DS-SS for various block lengths, (SNR=10 dB, SIR=1 dB,

^ ^⁰^.⁵

and

block length=300-1400 bits). 73

Figure C.4 The performance of interleavers in convolutional encoded DS-SS for various block lengths, (SNR=10 dB, SIR=2 dB,

^ ^⁰^.⁵

and block length=300-1400 bits). 74

Figure C.5 Performance of interleavers in convolutional encoded DS-SS for various block lengths, (SNR=10 dB, SIR=3 dB,

^ ^ ⁰^.⁵

and

block length=300-1400 bits). 75

Figure C.6 The performance of interleavers with convolutional encoder for DS-SS (SNR=10 dB, SIR=4 dB, ρ=0.5 and frame length=300-1400 bits). 76 Figure C.7 The performance of interleavers with convolutional encoder for DS-SS

(SNR=10 dB, SIR=5 dB, duty cycle jamming (ρ=0.5)

and frame length=300-1400 bits). 77

Figure C.8 The performance of interleavers with convolutional encoder for DS-SS (SNR=10 dB, SIR=6 dB, ρ=0.5, and frame length=300-1400 bits,

BER= x1.0e-003). 78

ix

(3)