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The surface morphology properties and respond illumination impact

of ZnO/n-Si photodiode by prepared atomic layer deposition

technique

I. Orak

a,b

, A. Kocyigit

c,*

, A. Turut

d

aBing€ol University, Vocational School of Health Services, 12000, Bing€ol, Turkey

bBing€ol University, Faculty of Sciences and Arts, Department of Physics, 12000, Bing€ol, Turkey

cIgdir University, Engineering Faculty, Department of Electrical Electronic Engineering, 76000, Igdir, Turkey

dIstanbul Medeniyet University, Faculty of Engineering and Natural Sciences, Engineering Physics Department, TR-34700, Istanbul, Turkey

a r t i c l e i n f o

Article history: Received 23 June 2016 Received in revised form 26 August 2016 Accepted 28 August 2016 Available online 29 August 2016

Keywords: ZnO/n-Si device Photodiode Photovoltaics

I-V and C-V characteristics Memristors

a b s t r a c t

The ZnO layer onto n-Si has been formed by atomic layer deposition technique. Afinal film thickness of 10 nm has been obtained by the resulting ZnOfilm growth rate of about 1.45 Å per cycle. The crystal structures of the ZnO layer were acquired by X-ray diffractometer (XRD) and it could be seen ZnO peaks from XRD patterns. The surface of ZnO thinfilm onto the n-Si could be seen with Atomic Force Micro-scopy (AFM) images and it were obtained homogenous and smooth surface. The I-V measurements were performed2V to þ2 V under dark and light, C-V measurements were performed changing 10 kHz to 2 MHz frequency and2 V to þ2 V bias voltage at room temperature. The device has the saturation current value of 8.99 109A. The values of ideality factor (n) and the barrier height (Ф

b) have been found to be 2.49 and 0.77 eV by using the thermionic emission theory, respectively. In addition, the barrier height ðФbÞ and the series resistance (Rs) have been also acquired from Cheung's functions. The photovoltaic parameters of device; short circuit current (Isc), open circuit voltage (Voc),fill factor (FF) and conversion efficiency (ƞ) were taken as 342 mV, 34.7 mA, 32% and 0.48% under 100 mW/cm2light intensity, respectively. The CeV and GeV plots of device almost have peaks in all frequencies except for 2 MHz frequency. The device also behaved like memristor at 500 kHz dual CeV measurements under dark and light but has not wide memory window. It has been concluded that the device can be used as photodiode at room temperature because of small saturation current and good rectifying behavior and it may be improved photovoltaic, capacitor and memristor properties of Au/ZnO/n-Si device in the future.

© 2016 Elsevier B.V. All rights reserved.

1. Introduction

Zinc Oxide (ZnO) is a member of Transparent Conductive Oxide (TCO)[1e3]and has high direct band gap (3.37 eV), large exciton binding energy (60 meV) and very promising properties such as low-costs, non-toxicity and low temperature deposition[4]. ZnO also has using areas in technology such as solar cells[5], chemical sensors[6,7], varistors[8], light-emitting diodes[9], UV photo de-tectors[10]and laser diodes[11].

There is a lot of technique to obtain the ZnO coatings. We have synthesized ZnO thinfilms on the n-Si substrates by atomic layer deposition (ALD) technique. The ALD has very good advantages

such as large area uniformity, definite thickness control, highly protective deposition. The ALD can be applied under low temper-ature growth which is very important for the fabrication of low cost andflexible electronics[12].

ZnO has been studied by different researchers to develop its behaviors in technological applications. Bedia et al. [13] have investigated ZnO/p-Si heterojunction for solar cell applications and reported that the diode properties of junctions were not ideal. H. Y. Kim et al.[14]have used ZnO thinfilm on n and p-type Si wafer to found photoresponse properties of Si detectors. ZnO based de-tectors have been strong rectifying properties and high photo-response depending on ZnO structures of devices. Yıldırım et al.

[15] have reported temperature-dependent currentevoltage (I-V) characteristics of Zn/ZnO/n-Si structure and structure has rectifying property and an uniform surface morphology. Yilmaz and Aydogan

* Corresponding author.

E-mail address:adem.kocyigit@igdir.edu.tr(A. Kocyigit).

Contents lists available atScienceDirect

Journal of Alloys and Compounds

j o u rn a l h o m e p a g e :h t t p : / / w w w . e l s e v i e r . c o m / l o c a t e / j a l c o m

http://dx.doi.org/10.1016/j.jallcom.2016.08.295

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[16]have explained some properties of un-doped and Mn-doped ZnO nanocrystalline thinfilms and ZnO/n-Si heterojunction. The diode parameters such as ideality factor and barrier height of ZnO/ n-Si heterojunction have been calculated from its IeV and capacitance-voltage (CeV) measurements. Also, Kumar et al.[17,18]

have investigated aluminum and boron co-doped films on sub-strate and p-Si subsub-strate and characterized thefilms for compati-bility of technological applications of ZnO. The aim of this study is to investigate the suitability of Au/ZnO/n-Si device for advanced technological applications such as diode, fotodiode, memristor and capacitor etc.

2. Experimental details

n-type Si wafer was used for obtaining of the ZnO/n-Si device. Its orientation and carrier concentration were (100) direction and 7.3 1015cm3, respectively in respect to producer. Initially the

wafer was degreased in sequence with methanol and acetone for 3 min and then it was disintegrated 1.0 1.0 cm2pieces. One of the

obtaining pieces were etched to remove the surface damages and undesirable impurities with H2SO4:H2O2:H2O (5:1:1) for 1 min. It

was vaporized gold thermally for ohmic contact on the one side of the piece of wafer. Obtained n-Si/Au was annealed in N2

atmo-sphere for 3 min at 450C. During the annealing process, N2

at-mosphere and 450C were used to prevent the oxidation on the surface and provide occurring of ohmic contact between n-Si and Au, respectively. The thickness of metal layer was controlled using a quartz thickness monitor placed in close proximity to the Si sample. ZnO deposition was achieved by Atomic layer deposition (ALD) technique on n-type Si with Savannah 100 thermal ALD reactor (Cambridge Savannah 100 ALD system) using diethylzinc and water vapor using as zinc and oxygen precursors, respectively and sub-strate temperature was fixed at 180 C. The resulting ZnOfilm

growth rate was about 1.45 Å per cycle andfinal thickness of film was 10 nm. After then Au metallic contact was evaporated onto the ZnO layer. Schematic diagram of Au/ZnO/n-Si device has been shown inFig. 1.

XRD patterns and AFM measurements were obtained by Bruker D8 Discover and PSIA XE-100E model, respectively. The IeV mea-surements were attained by use of a Keithley 2400 Picoammeter/ Voltage Source. The photovoltaic measurements were performed Solar Simulator which was called C01NC-16S-150-002. The CeV and GeV measurements of the device was carried out by using HP 4192 A LF Impedance Analyzer.

3. Result and discussion

X-ray diffractometer patterns of the ZnO layer could be seen in

Fig. 2 for wide angle ranges. There are three peaks referring to hexagonal structure of ZnO thin film; (100), (103) and (201)

[19e21]. Preferred orientation of thefilm is (201) peak and very intense. This intensity confirms that very thin layer and like single

crystal structure of ZnO layer[22].

2D and 3D AFM images of the surface of ZnO thinfilm onto the n-Si as scanning at 0.8

m

 0.8

m

m and 8

m

 8

m

m areas could be seen inFig. 3for surface morphology of structure. There is good homogeneity and uniform distribution which consists of spheroid shaped nanocrystallites on the surface of the device without any holes and cracks. RMS roughness value of the device is about 3.26 nm. This RMS value is very small and can be compared to literature for ZnO[12,23].

Semi-logarithmic I-V characteristic of Au/ZnO/n-Si device have been shown inFig. 4under dark and light conditions. Device has very good rectifying property, very small saturation current (I0)

value of 8.99 109A compared with other reports at the room

temperature and also exhibit photodiode behaviors[4,24,25]. If the device is illuminated by light, extra free carriers (electron-hole pairs) occurs in the device. These carriers increase the current in reverse region depending on illumination[26].

The I-V measurements could be used to reveal diode character-ization parameters based on thermionic emission theory. By use of the thermionic emission theory, the ideality factor and barrier height can be acquired from the slope and the current axis intercept of the linear region the forward bias IeV plot, respectively[27]. The current I is given by below equation in this theory;

I¼ I0exp  qV nkT  1 exp  qV nkT  (1) where I0is obtained from the intercept of the linear portion of lnI

versus V plot at V¼ 0, and is written as

I0¼ AA*T2exp  qФb kT  (2) in here; q is charge of electron, V is the applied bias voltage, K is Boltzmann's constant, T is the temperature (¼300 K), A* is

Richardson constant (A*¼ 112 A cm2K2for n-type Si), A is the

area of diode (¼7.85  103cm2),Ф

bis the barrier height at zero

bias and n is the ideality factor of the device. The ideality factor (for V 3kT/q) and barrier height specified from the forward bias lnIeV characteristics by use of the relations (1) and (2) can be changed like this:

Fig. 1. Schematic diagram of Au/ZnO/n-Si device.

Fig. 2. XRD patterns of ZnO layer obtained by ALD on Si. I. Orak et al. / Journal of Alloys and Compounds 691 (2017) 873e879

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n¼ q kT  dV dlnI  (3) and Фb¼ kT q ln  A*AT2 I0  (4) In respect to above last two relations, n andФbvalues of the Au/

ZnO/n-Si device were accounted as 2.49 and 0.77 eV in dark, 2.13 and 0.75 eV in light condition at room temperature, respectively. If n equals one, pure thermionic emission happens but n is usually greater than unity. A high ideality factor which is bigger than one could be ascribed to different things in the device for instance interface states[28], barrier inhomogeneity[29], image-force effect

[30], series resistance [31], tunneling process [32] and non-uniformity distribution of the interfacial charges[33]. In here, it can be attributed dominantly to interfacial layer and barrier in-homogeneity because of presence ZnO between the metal and semiconductor.

The series resistance (Rs), andФbcould be determined also using

Cheung's functions [34]. For a Schottky device which has series resistance, the clear amount current of the device is due to thermionic emission, it has been expressed as follows[27e30]:

I¼ I0exp qðV  IRnkT s  

(5) for Cheung's functions [35], where IRs which is stated dropping

voltage which is attributed the presence of series resistance in the device. This series resistance could be found from the aid of next

Fig. 3. AFM images in 2D and 3D graphs of the surface of ZnO thinfilm onto the n-Si at 0.8 and 8mm square.

Fig. 4. Semilogaritmic reverse and forward bias I-V characteristic of the Au/ZnO/n-Si device under dark and light conditions.

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Cheung's expressions[27]: dV dðlnIÞ¼ IRsþ nkTq (6) HðIÞ ¼ V  n  kT q  ln  I AA*T2  (7) where H(I) can be written as:

HðIÞ ¼ IRsþ nФb (8)

By using Eq.(6), a straight line is obtained the downward curve data of the forward bias IeV measurements. Consequently, the plot of dV/d(lnI) versus I is linear and give Rsand nkT/q values from the

slope and y-axis intercept of this plot, respectively. By use of the ideality factor found from Eq.(6)and downward curve data in the semi-log forward bias IeV measurements in Eq.(7), a plot of H(I) vs. I respect to Eq.(8)give straight line, also. In here, y-axis intercept equal to nФband slope of this plot also ensures a different obtaining

of Rswhich could be controlled the accuracy of Cheung

approxi-mation[34].

The graphs of dV/d(lnI) vs. I and H(I) vs. I have been attained from the forward bias currentevoltage measurements of the Au/ ZnO/n-Si device at room temperature under dark and shown in

Fig. 5. The values of n and Rs were calculated as n¼ 2.35 and

Rs¼ 279

U

in dark from dV/d(lnI) vs I. From the H(I) versus I plot, the

values ofФband Rswere accounted as 0.42 eV and 889

U

,

respec-tively. It can be seen clearly that the worth of series resistance ac-quired from the H(I)eI curve is in close harmony with the value found from the dV/d(lnI)eI plot. This close series resistance values verifies accuracy of the Cheung approach.

It could be seen that there is a slightly discrepancy between the ideality factors attained from the Cheung's function and thermionic emission theory of the same characteristics. This discrepancy can be depended some effects such as series resistance, Schottky bar-rier height[15].

The device has shown photovoltaic behaviors which could be proved determining some parameters such as short circuit current density (Jsc) and open circuit voltage (Voc). According toFig. 6under

100 mW/cm2light intensity, these values were found as 342 mV and 4.43 mA/cm2, respectively. Photovoltaic behaviors of a Schottky device can be expressed next sentences. If a negative bias of the device is increased with the light, it can be said that light is causing the carriers which electron-hole pairs are generated in the

depletion region of semiconductor to jump over the barrier height. For this reason, photons from light source should have greater energy than band gap energy of semiconductor (Eg). In here, the

negative bias current have been risen with illumination could be seen inFig. 4 [36]. In other words, electronehole pairs or carriers and their accumulation at the barrier have been obtained because of the potential difference with illumination [37]. The other photovoltaic parameters such asfill factor and power conversion efficiency were accounted from below relations.

Thefill factor (FF) is accounted as[28]: FF¼JmVm

JscVoc

(12) The power conversion efficiency,

h

p, is[38]

h

p¼ JmVm

P0

(13) in here JmVmis called maximum power point of J-V graphs and P0is

light density which is 100 mW/cm2. Fill factor and power conver-sion efficiency are very sensitive according to open-circuit voltage (Voc) and short circuit current density (Jsc). FF and

h

pwas accounted

32% and 0.48%, respectively. The Au/ZnO/n-Si device has a low

Fig. 5. dv/dlnI-I and H(I)-I graphs of Au/ZnO/n-Si device in dark.

Fig. 6. The current-voltage (IeV) characteristic under illumination for Au/ZnO/n-Si device.

Fig. 7. The capacitance-voltage (CeV) characteristic Au/ZnO/n-Si device. I. Orak et al. / Journal of Alloys and Compounds 691 (2017) 873e879

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conversion efficiency and low fill factor which is ascribed to series resistance or recombination current in the space charge region of the device but its conversion efficiency could be increased more with antireflection coating and other suitable optimization[37].

Fig. 7has shown C-V characteristic of Au/ZnO/n-Si device for different frequencies. It could be said from thisfigure, device has been influenced the changing frequency and bias voltage. The capacitance values have decreased with increasing (10 kHze2 MHz) frequencies in the accumulation and depletion regions. These decreasing attributed to the interface states[39]. In the high frequencies, interface states cannot follow ac signals and cause low capacitance values[40]. The values of capacitances have changed increasing frequency from forward to reverse bias voltage.

Fig. 8has indicated G-V characteristics of Au/ZnO/n-Si device for alteration frequency (Changing 10 kHz to 2 MHz) and bias voltage (2 V to þ2 V). It can be seen fromFig. 8that conductance values increased with increasing frequencies to 2 MHz. It could be observed peaks in the depletion region in all frequencies and these peaks have tendency to reverse bias voltage with increasing frequency.

The C2eV plots exhibit a straight line in a wide bias range, and diffusion potential has been found from the extrapolation of this line to the voltage axis (intercept potentials have been shown in

Table 1). Owing to slope of this line could be accounted different

parameters such as barrier height, fermi level, maximum electric filed and doping concentration [40]. These parameters could be seen in Table 1. The C2eV plots of the Au/ZnO/n-Si device at different frequencies have been given inFig. 9. It has been observed that the voltage axis extrapolation have changed from the reverse bias to forward bias by increasing frequency.

Cef and Gef plots of Au/ZnO/n-Si device at different voltage from 0 to - 0.6 V with 0.12 steps can be seen inFig. 10. The capac-itance values decreased with increasing frequency up to high voltage values while they are constant at low voltages. When conductance values have not shown increasing with increasing frequency at low voltage values, they have increased with increasing voltage up to 0.6 V.

The memristor behavior of Au/ZnO/n-Si device has been inves-tigated in dark and light conditions. It has been seen inFig. 11that the dual capacitance and conductance characteristics have been observed at 500 kHz. Memristor has low power and nonvolatile operation, variety of physical mechanisms and potentially high density, placing advanced components of future computing sys-tems[41]. It could be said fromFig. 11that there is no wide memory windows at dark and light conditions of Au/ZnO/n-Si device. It may be discovered and improved of memory windows of device.

The different parameters obtained from CeV measurements have been given inTable 1for the Au/ZnO/n-Si device. It can be said

Fig. 8. The conductance-voltage (GeV) characteristics of Au/ZnO/n-Si device.

Table 1

The some experimental parameters obtained from CeV measurements.

f (kHz) Nd(1015cm3) Vi(V) EF(meV) DFb(meV) Fb(eV) Em(104V/m)

10 3.154 1.89 168 22.69 2.061 4.256 20 2.974 1.77 169 21.99 1.943 3.999 30 2.898 2.00 170 22.53 2.173 4.196 50 2.789 1.90 171 22.03 2.055 4.012 70 2.733 1.88 172 21.86 2.016 3.951 100 2.669 1.84 172 21.62 2.016 3.863 200 2.669 1.77 172 21.41 1.947 3.789 300 2.480 1.78 174 21.05 1.959 3.662 400 2.439 1.75 175 20.87 1.930 3.601 500 2.408 1.76 175 20.83 1.940 3.589 600 2.390 1.76 175 20.80 1.940 3.575 700 2.378 1.80 175 20.89 1.980 3.607 800 2.373 1.79 175 20.85 1.970 3.592 900 2.370 1.79 175 20.84 1.970 3.590 1000 2.367 1.86 175 21.03 2.040 3.657 2000 2.621 2.34 173 22.85 2.516 4.317

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from this table that Nd values of devices have decreased with

increasing frequency [39]. EF levels increased nearly up to high

frequencies and Фb values changed with changing frequency

differently. Maximum electricfield values (Em) also were influenced

increasing frequency.

4. Conclusion

Au/ZnO/n-Si device were studied with XRD, AFM, I-V and C-V measurements performed changing from 10 kHz to 2 MHz and2 V to þ2 V bias voltages at room temperature. It could be seen ZnO peaks only from XRD patterns. The device has uniform surface morphology (3.26 nm RMS value) and the lowest saturation current value has at room temperature comparing the literature. The ideality factor n and Фb values were found to be 2.49 and 0.77 eV using the thermionic emission theory. TheФband Rswere

obtained from Cheung's functions. n, Фb; Rs(dV/d(lnI) vs I) and Rs

(H(I) vs I) were taken as 2.35, 0.43 eV, 279

U

and 889

U

, respectively. The lowest series resistances were acquired for ZnO/n-Si device. The photovoltaic parameters; short circuit current (Isc), open circuit

voltage (Voc), fill factor (FF) and conversion efficiency (ƞ) were

attained as 342 mV, 34.7

m

A, 32% and 0.48% under 100 mW/cm2 light intensity, respectively. The CeV and GeV plots of device almost have peaks in all frequencies. The memristor property of the

device has been seen at dual CeV measurements under dark and light but has not wide memory window. It may be improved diode, capacitor, photovoltaic and memristor properties of the Au/ZnO/n-Si device in the future investigations.

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Şekil

Fig. 1. Schematic diagram of Au/ZnO/n-Si device.
Fig. 3. AFM images in 2D and 3D graphs of the surface of ZnO thin film onto the n-Si at 0.8 and 8 m m square.
Fig. 6. The current-voltage (IeV) characteristic under illumination for Au/ZnO/n-Si device.
Table 1 ). Owing to slope of this line could be accounted different
+2

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