Önerilen çözümü birçok yönden genişletmek ve daha fazla sıcaklık duyarlılığı olan daha iyi bir çözüm tasarlamak mümkündür. BRAM yapısının zayıf noktalarını analiz edip bu bilgiyi de kullanarak daha gelişmiş bir kontrolcü tasarımı gelecekteki çalışmalar için bırakılmıştır. FPGA yongası üzerindeki BRAM bölgelerini analiz ederek ve FPGA üzerinde koşan uygulamanın taleplerini belirleyerek, uygulamayı belirli BRAM bölgelerine eşlemek ve hata olma olasılığı daha düşük olan bölgeleri kullanarak daha düşük güç tüketimi elde etmek mümkündür. Düşük besleme gerilimi kaynaklı hataların oluşumunu ortadan kaldırabilen daha akıllı bir analizör ile daha fazla güç tasarrufu sağlanabilir.
BRAM’lere ECC ekleyerek çalışma gerilimi düşürülmesi kaynaklı 1-bit hataları düzeltip güç tüketimini azaltma yöntemi [25]’de önerilmiştir. Bu yöntemi sıcaklığa bağlı olarak geliştirip değişen sıcaklığa göre ihtiyaç duyulan zamanlarda aktif olacak akıllı bir ECC yapısı ekleme çalışması sonraki çalışma olarak bırakılmıştır.
Çalışma gerilimi düşürülmesi işleminin FPGA’in diğer gerilimleri üzerindeki etkilerinin araştırılması ve bu etkilerin analizi sonrası bu gerilimlerde de çalışma gerilimi düşürülmesi yapılarak daha faz güç kazanımı sağlanıp sağlanamayacağının çalışması gelecek çalışmalardan biri olabilir.
KAYNAKLAR
[1] Lane, N. D., et al., (2016). Deepx: A software accelerator for low-power deep learning inference on mobile devices, Proceedings of the 15th
International Conference on Information Processing in Sensor Networks, Vienna, Austria.
[2] Oskouei, S. S. L., Golestani, H., Hashemi, M., Ghiasi, S., (2016). CNNdroid: Gpu-accelerated execution of trained deep convolutional neural networks on android, Proceedings of the 24th ACM international
conference on Multimedia, San Francisco, USA.
[3] Zhang, C., et al., (2015). Optimizing FPGA-based accelerator design for deep convolutional neural networks, Proceedings of the 2015 ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays,
California, USA.
[4] Canis, A., et al., (2011). LegUp: high-level synthesis for FPGA-based processor/accelerator systems, Proceedings of the 19th ACM/SIGDA
international symposium on Field programmable gate arrays,
California, USA.
[5] Suda, N., et al., (2016). Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks, Proceedings of the 2016
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, California, USA.
[6] Chang, K. K., et al., (2017). Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms, Proceedings of the ACM on Measurement and Analysis of
Computing Systems 1.1, New York, USA.
[7] Chang, K. K., et al., (2018). Voltron: Understanding and Exploiting the Voltage- Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency, arXiv preprint arXiv:1805.03175.
[8] Tovletoglou, K., et al., (2018). Measuring and exploiting guardbands of server- grade ARMv8 CPU cores and DRAMs, 2018 48th Annual IEEE/IFIP
International Conference on Dependable Systems and Networks Workshops (DSN-W), Luxembourg.
[9] David, H., Fallin, C., Gorbatov, E., Hanebutte, U. R., Mutlu, O., (2011). Memory power management via dynamic voltage/frequency scaling,
Proceedings of the 8th ACM international conference on Autonomic computing, Karlsruhe, Germany.
[10]<https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/p t/stratix-10-product-table.pdf>, Alındığı tarih:03.11.2019.
60
[11] <http://jjmk.dk/MMMI/PLDs/FPGA/fpga.h11.jpg>, Alındığı tarih:03.11.2019. [12] <https://docs.microsoft.com/tr-tr/azure/machine-learning/service/how-to-deploy-
fpga-web-service>, Alındığı tarih:03.11.2019.
[13]<https://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010- XC7Z020-Data-Sheet.pdf>, Alındığı tarih:03.11.2019.
[14]<https://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug 850-zc702-eval-bd.pdf>, Alındığı tarih:03.11.2019.
[15]<https://www.nandland.com/articles/block-ram-in-fpga.html>, Alındığı tarih:03.11.2019.
[16]<https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Ov erview.pdf>, Alındığı tarih:03.11.2019.
[17]<https://www.xilinx.com/support/documentation/ip_documentation/bram_block. pdf>, Alındığı tarih:03.11.2019.
[18]<https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_M emory_Resources.pdf>, Alındığı tarih:03.11.2019.
[19] The Design Warrior’s Guide to FPGAs Devices, Tools and Flows. ISBN 0750676043, 2004.
[20] Lorch, J. R., Smith, A. J., (2001). Improving dynamic voltage scaling algorithms with PACE, ACM SIGMETRICS Performance Evaluation Review, Vol. 29. No. 1.
[21] Bacha, A., Teodorescu, R., (2013). Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors, ACM SIGARCH
Computer Architecture News, Vol. 41. No. 3.
[22] Leng, J., Buyuktosunoglu, A., Bertran, R., Bose, P., Reddi, V. J., (2015). Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach, 2015 48th Annual IEEE/ACM International Symposium on
Microarchitecture (MICRO), Waikiki, HI, USA.
[23] Mei, X., Yung, L. S., Zhao, K., Chu, X., (2013). A measurement study of GPU DVFS on energy conservation, Proceedings of the Workshop on Power-
Aware Computing and Systems, Pennsylvania, USA.
[24] Salami, B., Unsal, O. S., Kestelman, A. C., (2018). Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-chip Memories, 51st
Annual IEEE/ACM International Symposium on Microarchitecture (MICRO),.
[25] Salami, B., Unsal, O. S., Kestelman, A. C., (2019). "Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Errors," 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), IEEE, 2019.
[26] Ahmed, I., Zhao, S., Trescases, O, Betz, V., (2018). Automatic Application- Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37.12: 3095-3108.
[27] Yang, Y., Li., K. S., (2009). Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement, Proceedings of the 2009
Asia and South Pacific Design Automation Conference, Yokohama,
Japan.
[28] Lefurgy, C. R., et al., (2011). Active management of timing guardband to save energy in POWER7, 2011 44th Annual IEEE/ACM International
Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil.
[29] Bowhill, B., et al., (2015). The Xeon® processor E5-2600 v3: A 22 nm 18-core product family, IEEE Journal of Solid-State Circuits 51.1 (2015): 92- 104.
[30] Zhang, J., Rangineni, K., Ghodsi, Z., Garg, S., (2018). ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators, Proceedings of
55th Design Automation Conference (DAC), San Francisco, California,
USA.
[31] Yang, L., Murmann., B., (2017). SRAM voltage scaling for energy-efficient convolutional neural networks, in Proceedings of the 18th International
Symposium on Quality Electronic Design (ISQED), Santa Clara, CA,
USA.
[32] Nunez-Yanez, et al., (2016). Energy optimization in commercial FPGAs with voltage, frequency and logic scaling, IEEE Transactions on Computers Volume: 65 , Issue: 5.
[33] Yalcin, G., Islek, E., Tozlu, O., Reviriego, P., Cristal, A., Unsal, O. S., Ergin, O., (2014). Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches, in Proceedings of the 20th IEEE International
Symposium on On-Line Testing Symposium (IOLTS), Girona, Spain.
[34]<http://www.ti.com/tool/fusion_digital_power_designer?keyMatch=fusion%20di gital%20powe%20rdesigne&tisearch=Search-EN-Everything,
Alındığı tarih:03.11.2019.
[35] < http://pmbus.org>, Alındığı tarih:03.11.2019.
[36] Levine, J. M., et al., (2014). Dynamic Voltage & Frequency Scaling with Online Slack Measurement, 2014 ACM/SIGDA international symposium on
Field-programmable gate arrays, California, USA.
[37] Ahmed, I., et al., Measure twice and cut once: Robust dynamic voltage scaling for FPGAs, 2016 26th International Conference on Field
Programmable Logic and Applications (FPL), Lausanne, Switzerland.
[38] Chow, C. T., et al., (2005). Dynamic voltage scaling for commercial FPGAs,
2005 IEEE International Conference on Field-Programmable Technology, Singapore.
[39] Nabina, A., Nunez-Yanez, J. L., (2012). Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform, TRETS, vol. 5, no. 4, pp. 20:1–20:22.
62
[40] Ahmed, I., Zhao, S., Meijers, J., Trescases, O., Betz, V., (2018). Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs, 2018
28th International Conference on Field Programmable Logic and Applications (FPL), Dublin.
[41] Morita, Y., Fujiwara, H., Noguchi, H., Iguchi, Y., Nii, K., Kawaguchi, H., Yoshimoto, M. (2007). Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Transactions, 90-C, 1949-1956.
[42] <https://allthingsvlsi.wordpress.com/2013/04/19/6t-sram-operation/>, Alındığı tarih:03.11.2019.
[43] Vătăjelu, E. I., Figueras, J., (2010). Statistical analysis of SRAM parametric failure under supply voltage scaling, 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), Cluj-Napoca, 2010, pp. 1-6.
[44] Vătăjelu, E. I., Figueras, J., (2011). Statistical analysis of 6T SRAM data retention voltage under process variation, 14th IEEE International
Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, 2011, pp. 365-370.
[45] Kumar, A., Rabaey, J., Ramchandran, K., (2009). SRAM supply voltage scaling: A reliability perspective, 2009 10th International Symposium
on Quality Electronic Design, San Jose, CA, 2009, pp. 782-787.
[46] Nunez-Yanez, J., (2013). Energy Proportional Computing in Commercial FPGAs with Adaptive Voltage Scaling, FPGAworld '13 Proceedings of
the 10th FPGAworld Conference, Stockholm, Sweden.
[47] Salami, B., Unsal, O. S., Kestelman, A. C., (2018). Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories, 2018
51st Annual IEEE/ACM International Symposium on
Microarchitecture (MICRO), Fukuoka, 2018, pp. 724-736.
[48] Salami, B., Unsal, O. S., Kestelman, A. C., (2018). Fault Characterization Through FPGA Undervolting, 2018 28th International Conference on
Field Programmable Logic and Applications (FPL), Dublin, 2018, pp.
85-853.
[49] Khaleghi, B., Rosing, T. Š., (2019). Thermal-Aware Design and Flow for FPGA Performance Improvement, 2019 Design, Automation & Test in Europe
Conference & Exhibition (DATE), Florence, Italy, 2019, pp. 342-347.
[50]<https://www.xilinx.com/support/documentation/application_notes/xapp555- Lowering-Power-Using-VID-Bit.pdf>, Alındığı tarih:03.11.2019. [51]<http://www.altima.jp/products/devices/stratix/download/wp-01200-power-
performance-zettabyte-generation-10.pdf>, Alındığı tarih:03.11.2019. [52]<https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Ov
erview.pdf>, Alındığı tarih:03.11.2019.
[54] Neshatpour, K., Burleson, W., Khajeh, A., Homayoun, H., (2018). Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence, in IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 778-791.
[55] Sassone, A., et al., (2012). Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks, 2012 Design,
Automation & Test in Europe Conference & Exhibition (DATE),
ÖZGEÇMİŞ
Ad-Soyad : Fulya AĞIRNAS
Uyruğu : T.C.
Doğum Tarihi ve Yeri : 03.07.1988, Antakya
E-posta : fagirnas@etu.edu.tr
ÖĞRENİM DURUMU:
Lisans : 2011, Orta Doğu Teknik Üniversitesi, Mühendislik Fakültesi, Elektrik ve Elektronik Mühendisliği (3,29/4,00)
Yüksek Lisans : 2019, TOBB Ekonomi ve Teknoloji Üniversitesi, Mühendislik Fakültesi, Bilgisayar Mühendisliği
MESLEKİ DENEYİM VE ÖDÜLLER:
Yıl Yer Görevler
2009 2009 2010 2010 2011-Halen 2017-2019
Tübitak Uzay Teknolojileri Araştırma Enstitüsü
Türk Havacılık ve Uzay Sanayi (TAİ) ASELSAN A.Ş ASELSAN A.Ş ASELSAN A.Ş TOBB ETÜ Stajyer Stajyer Stajyer Aday Mühendis Mühendis ARGE Burslu Yüksek Lisans Öğrencisi YABANCI DİL: İngilizce (İyi), Almanca(Başlangıç)
TEZDEN TÜRETİLEN YAYINLAR, SUNUMLAR VE PATENTLER:
Ağırnas, F., Say, F., Ergin, O. (2019). FPGA BRAM’lerde Çalışma Gerilimi Düşürülmesine Sıcaklığın Etkileri. İşlemci Tasarımı Çalıştayı 2019, İstanbul, Türkiye.