Digital Controller Unit

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External leakage inductor will be designed considering energy storage and core losses. Since the current flowing in the secondary will be very high, the core used for the inductor must not saturate and the flux swing should not be very high to increase core losses. That is why a core manufactured from a low permeability, distributed airgap material is chosen for the application. Core is made from MPP material from Magnetics Inc. and its part number is 55550A2. It has low permeability at 26 µ, and presents low core losses. Using (5.5) required number turns can be calculated. AL value of 55550A2 is 28±8% nH/T², and for the specified 15 µH of inductance, required number of turns is 24. The current flowing through inductor and transformer secondary is identical. Thus, 20 strands of 0.5 mm diameter wire that is used in transformer secondary will be used here as well. However, during the mechanical construction of the inductor it was realized that winding window cannot accommodate the calculated number of turns; thus number of turns had to be decreased to 22. Resulting inductance is measured as 14.50 µH. The final look of the inductor is given in Figure 5.5.

Figure 5.5. Leakage inductor

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Figure 5.6. Digital controller unit

Digital control ground is referenced to DC side ground of the charger. That is why voltage and current measurements from AC side are obtained in an isolated fashion. Control algorithm running in the DCU makes use of the voltage and current measurements taken from both AC and DC side and calculates the duty cycle of the DC side switches cycle-by-cycle. Since the DCU is used to control two charger modules simultaneously, the voltage and current measurements should be read from different ADC channels. To achieve this with identical charger modules, outputs of voltage and current transducers are routed to two different ADC channels in a double pole single throw switch like manner.

Enhanced pulse width modulation (EPWM) units in the DCU are used to drive semiconductor switches. AC side switches are driven by complementary signals with 50%

duty cycle, so that is why just one EPWM unit with two outputs is sufficient to drive AC

Table 5.2. Specifications of digital controller unit Central Processing Unit (CPU) TMS320C28x series CPU operating at 150 MHz

Clock and System Control

 On-Chip Oscillator

 Dynamic PLL Ratio Changes Supported

 Watchdog Timer

 Three 32-bit Timers Memory

 256K × 16 Flash

 34K × 16 SARAM

 8K × 16 Boot ROM

Enhanced Control Peripherals

 12 PWM Outputs

 Six Event Capture Inputs

 Two Quadrature Encoder Interfaces Analog-to-Digital Converter

(ADC)

 12-bit resolution

 Two Sample and Hold

 12,5 MSPS Throughput General Purpose Input/Output

(GPIO) 88 Multiplexed GPIO Pins With Input Filtering Serial Port Peripherals

 One Inter-Integrated-Circuit Bus

 One Serial Peripheral Interface

 Three Universal Asynchronous Receiver/Transmitter Modules

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side switches in both modules. However, DC side switches require complex gate drive signals for the system to operate properly, and because of that two independent EPWM units with four PWM outputs in total are dedicated to each DC full bridge for both charger modules. In total five EPWM units of the DCU are utilized for the control of semiconductor switches. EPWM5 is dedicated to AC side switches of the both charger modules, EPWM1 and EPWM3 are dedicated to DC side switches of the Module 1 and EPWM2 and EPWM4 are dedicated to the Module 2.

Time base counters of the EPWM units are counting at the operating frequency of the DCU, which is 150 MHz. For 25 kHz switching frequency, this translates to a time base period value of 6000. Also all the time base counters are synchronized with each other to start counting at the same time. Compare A (CMPA) and Compare B (CMPB) registers in EPWM units are used to achieve various PWM outputs. For EPWM1 and EPWM3 outputs, dead band module in the DCU is utilized to achieve precise dead band control. Dead band for AC side gate drive signals are achieved with integrated dead band control of the gate drive circuits. Time base counter and PWM adjusting scheme is clearly illustrated with color coded symbols in Figure 5.7 for Module 1.

CMPA and CMPB values of EPWM1 and EPWM3 are calculated cycle-by-cycle based on the available information on AC and DC voltage levels. Closed loop control algorithm determines the phase-shift for the desired grid power or charging current. Necessary precautions are taken to ensure stable operation of the control algorithm; for example, by saturating the output of closed loop control algorithm not to exceed the maximum phase shift value.

To calculate real, reactive and apparent power of the AC side, a square wave synchronized with the zero crossings of AC voltage is fed through a GPIO pin of the DCU. GPIO input filtering is utilized to get rid of the possible high frequency noise and jitter from the input signal. Moreover, necessary algorithms are developed for calculating root mean squares of voltage and current values.

Input and output current values of both chargers are used for protection purposes in overcurrent events. To achieve this purpose a gate driver module is selected with an external enable/disable pin. When either current of the charger exceeds the pre-specified threshold value, overcurrent flag is set and the gate driver modules are disabled through this

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enable/disable pin via GPIO pins of the DCU. Overcurrent flag is not cleared and gate drivers are not enabled until charger is reset externally.

Time Base Counter

6000

CMPA= 3000

EPWM5A

EPWM5B

EPWM1A

EPWM1B

CMPA CMPB

dead-time dead-time

CMPA CMPB

EPWM3A

EPWM3B

phase shift

CMPA CMPB

CMPA CMPB

6000

dead-time dead-time

phase shift

t

t

t

t

t

t

t

CMPA= 3000

Figure 5.7. EPWM scheme utilized in the DCU